1//==- llvm/CodeGen/MachineMemOperand.h - MachineMemOperand class -*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineMemOperand class, which is a
10// description of a memory reference. It is used to help track dependencies
11// in the backend.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_MACHINEMEMOPERAND_H
16#define LLVM_CODEGEN_MACHINEMEMOPERAND_H
17
18#include "llvm/ADT/BitmaskEnum.h"
19#include "llvm/ADT/PointerUnion.h"
20#include "llvm/Analysis/MemoryLocation.h"
21#include "llvm/CodeGen/PseudoSourceValue.h"
22#include "llvm/CodeGenTypes/LowLevelType.h"
23#include "llvm/IR/DerivedTypes.h"
24#include "llvm/IR/LLVMContext.h"
25#include "llvm/IR/Metadata.h"
26#include "llvm/IR/Value.h" // PointerLikeTypeTraits<Value*>
27#include "llvm/Support/AtomicOrdering.h"
28#include "llvm/Support/Compiler.h"
29#include "llvm/Support/DataTypes.h"
30
31namespace llvm {
32
33class MDNode;
34class raw_ostream;
35class MachineFunction;
36class ModuleSlotTracker;
37class TargetInstrInfo;
38
39/// This class contains a discriminated union of information about pointers in
40/// memory operands, relating them back to LLVM IR or to virtual locations (such
41/// as frame indices) that are exposed during codegen.
42struct MachinePointerInfo {
43 /// This is the IR pointer value for the access, or it is null if unknown.
44 PointerUnion<const Value *, const PseudoSourceValue *> V;
45
46 /// Offset - This is an offset from the base Value*.
47 int64_t Offset;
48
49 unsigned AddrSpace = 0;
50
51 uint8_t StackID;
52
53 explicit MachinePointerInfo(const Value *v, int64_t offset = 0,
54 uint8_t ID = 0)
55 : V(v), Offset(offset), StackID(ID) {
56 AddrSpace = v ? v->getType()->getPointerAddressSpace() : 0;
57 }
58
59 explicit MachinePointerInfo(const PseudoSourceValue *v, int64_t offset = 0,
60 uint8_t ID = 0)
61 : V(v), Offset(offset), StackID(ID) {
62 AddrSpace = v ? v->getAddressSpace() : 0;
63 }
64
65 explicit MachinePointerInfo(unsigned AddressSpace = 0, int64_t offset = 0)
66 : V((const Value *)nullptr), Offset(offset), AddrSpace(AddressSpace),
67 StackID(0) {}
68
69 explicit MachinePointerInfo(
70 PointerUnion<const Value *, const PseudoSourceValue *> v,
71 int64_t offset = 0,
72 uint8_t ID = 0)
73 : V(v), Offset(offset), StackID(ID) {
74 if (V) {
75 if (const auto *ValPtr = dyn_cast_if_present<const Value *>(Val&: V))
76 AddrSpace = ValPtr->getType()->getPointerAddressSpace();
77 else
78 AddrSpace = cast<const PseudoSourceValue *>(Val&: V)->getAddressSpace();
79 }
80 }
81
82 MachinePointerInfo getWithOffset(int64_t O) const {
83 if (V.isNull())
84 return MachinePointerInfo(AddrSpace, Offset + O);
85 if (isa<const Value *>(Val: V))
86 return MachinePointerInfo(cast<const Value *>(Val: V), Offset + O, StackID);
87 return MachinePointerInfo(cast<const PseudoSourceValue *>(Val: V), Offset + O,
88 StackID);
89 }
90
91 /// Return true if memory region [V, V+Offset+Size) is known to be
92 /// dereferenceable.
93 LLVM_ABI bool isDereferenceable(unsigned Size, LLVMContext &C,
94 const DataLayout &DL) const;
95
96 /// Return the LLVM IR address space number that this pointer points into.
97 LLVM_ABI unsigned getAddrSpace() const;
98
99 /// Return a MachinePointerInfo record that refers to the constant pool.
100 LLVM_ABI static MachinePointerInfo getConstantPool(MachineFunction &MF);
101
102 /// Return a MachinePointerInfo record that refers to the specified
103 /// FrameIndex.
104 LLVM_ABI static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI,
105 int64_t Offset = 0);
106
107 /// Return a MachinePointerInfo record that refers to a jump table entry.
108 LLVM_ABI static MachinePointerInfo getJumpTable(MachineFunction &MF);
109
110 /// Return a MachinePointerInfo record that refers to a GOT entry.
111 LLVM_ABI static MachinePointerInfo getGOT(MachineFunction &MF);
112
113 /// Stack pointer relative access.
114 LLVM_ABI static MachinePointerInfo getStack(MachineFunction &MF,
115 int64_t Offset, uint8_t ID = 0);
116
117 /// Stack memory without other information.
118 LLVM_ABI static MachinePointerInfo getUnknownStack(MachineFunction &MF);
119};
120
121
122//===----------------------------------------------------------------------===//
123/// A description of a memory reference used in the backend.
124/// Instead of holding a StoreInst or LoadInst, this class holds the address
125/// Value of the reference along with a byte size and offset. This allows it
126/// to describe lowered loads and stores. Also, the special PseudoSourceValue
127/// objects can be used to represent loads and stores to memory locations
128/// that aren't explicit in the regular LLVM IR.
129///
130class MachineMemOperand {
131public:
132 /// Flags values. These may be or'd together.
133 enum Flags : uint16_t {
134 // No flags set.
135 MONone = 0,
136 /// The memory access reads data.
137 MOLoad = 1u << 0,
138 /// The memory access writes data.
139 MOStore = 1u << 1,
140 /// The memory access is volatile.
141 MOVolatile = 1u << 2,
142 /// The memory access is non-temporal.
143 MONonTemporal = 1u << 3,
144 /// The memory access is dereferenceable (i.e., doesn't trap).
145 MODereferenceable = 1u << 4,
146 /// The memory access always returns the same value (or traps).
147 MOInvariant = 1u << 5,
148
149 // Reserved for use by target-specific passes.
150 // Targets may override getSerializableMachineMemOperandTargetFlags() to
151 // enable MIR serialization/parsing of these flags. If more of these flags
152 // are added, the MIR printing/parsing code will need to be updated as well.
153 MOTargetFlag1 = 1u << 6,
154 MOTargetFlag2 = 1u << 7,
155 MOTargetFlag3 = 1u << 8,
156 MOTargetFlag4 = 1u << 9,
157
158 LLVM_MARK_AS_BITMASK_ENUM(/* LargestFlag = */ MOTargetFlag4)
159 };
160
161private:
162 /// Atomic information for this memory operation.
163 struct MachineAtomicInfo {
164 /// Synchronization scope ID for this memory operation.
165 unsigned SSID : 8; // SyncScope::ID
166 /// Atomic ordering requirements for this memory operation. For cmpxchg
167 /// atomic operations, atomic ordering requirements when store occurs.
168 unsigned Ordering : 4; // enum AtomicOrdering
169 /// For cmpxchg atomic operations, atomic ordering requirements when store
170 /// does not occur.
171 unsigned FailureOrdering : 4; // enum AtomicOrdering
172 };
173
174 MachinePointerInfo PtrInfo;
175
176 /// Track the memory type of the access. An access size which is unknown or
177 /// too large to be represented by LLT should use the invalid LLT.
178 LLT MemoryType;
179
180 Flags FlagVals;
181 Align BaseAlign;
182 MachineAtomicInfo AtomicInfo;
183 AAMDNodes AAInfo;
184 const MDNode *Ranges;
185
186public:
187 /// Construct a MachineMemOperand object with the specified PtrInfo, flags,
188 /// size, and base alignment. For atomic operations the synchronization scope
189 /// and atomic ordering requirements must also be specified. For cmpxchg
190 /// atomic operations the atomic ordering requirements when store does not
191 /// occur must also be specified.
192 LLVM_ABI
193 MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, LocationSize TS,
194 Align a, const AAMDNodes &AAInfo = AAMDNodes(),
195 const MDNode *Ranges = nullptr,
196 SyncScope::ID SSID = SyncScope::System,
197 AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
198 AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
199 LLVM_ABI
200 MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, LLT type, Align a,
201 const AAMDNodes &AAInfo = AAMDNodes(),
202 const MDNode *Ranges = nullptr,
203 SyncScope::ID SSID = SyncScope::System,
204 AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
205 AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
206
207 const MachinePointerInfo &getPointerInfo() const { return PtrInfo; }
208
209 /// Return the base address of the memory access. This may either be a normal
210 /// LLVM IR Value, or one of the special values used in CodeGen.
211 /// Special values are those obtained via
212 /// PseudoSourceValue::getFixedStack(int), PseudoSourceValue::getStack, and
213 /// other PseudoSourceValue member functions which return objects which stand
214 /// for frame/stack pointer relative references and other special references
215 /// which are not representable in the high-level IR.
216 const Value *getValue() const {
217 return dyn_cast_if_present<const Value *>(Val: PtrInfo.V);
218 }
219
220 const PseudoSourceValue *getPseudoValue() const {
221 return dyn_cast_if_present<const PseudoSourceValue *>(Val: PtrInfo.V);
222 }
223
224 const void *getOpaqueValue() const { return PtrInfo.V.getOpaqueValue(); }
225
226 /// Return the raw flags of the source value, \see Flags.
227 Flags getFlags() const { return FlagVals; }
228
229 /// Bitwise OR the current flags with the given flags.
230 void setFlags(Flags f) { FlagVals |= f; }
231
232 /// For normal values, this is a byte offset added to the base address.
233 /// For PseudoSourceValue::FPRel values, this is the FrameIndex number.
234 int64_t getOffset() const { return PtrInfo.Offset; }
235
236 unsigned getAddrSpace() const { return PtrInfo.getAddrSpace(); }
237
238 /// Return the memory type of the memory reference. This should only be relied
239 /// on for GlobalISel G_* operation legalization.
240 LLT getMemoryType() const { return MemoryType; }
241
242 /// Return the size in bytes of the memory reference.
243 LocationSize getSize() const {
244 return MemoryType.isValid()
245 ? LocationSize::precise(Value: MemoryType.getSizeInBytes())
246 : LocationSize::beforeOrAfterPointer();
247 }
248
249 /// Return the size in bits of the memory reference.
250 LocationSize getSizeInBits() const {
251 return MemoryType.isValid()
252 ? LocationSize::precise(Value: MemoryType.getSizeInBits())
253 : LocationSize::beforeOrAfterPointer();
254 }
255
256 LLT getType() const {
257 return MemoryType;
258 }
259
260 /// Return the minimum known alignment in bytes of the actual memory
261 /// reference.
262 LLVM_ABI Align getAlign() const;
263
264 /// Return the minimum known alignment in bytes of the base address, without
265 /// the offset.
266 Align getBaseAlign() const { return BaseAlign; }
267
268 /// Return the AA tags for the memory reference.
269 AAMDNodes getAAInfo() const { return AAInfo; }
270
271 /// Return the range tag for the memory reference.
272 const MDNode *getRanges() const { return Ranges; }
273
274 /// Returns the synchronization scope ID for this memory operation.
275 SyncScope::ID getSyncScopeID() const {
276 return static_cast<SyncScope::ID>(AtomicInfo.SSID);
277 }
278
279 /// Return the atomic ordering requirements for this memory operation. For
280 /// cmpxchg atomic operations, return the atomic ordering requirements when
281 /// store occurs.
282 AtomicOrdering getSuccessOrdering() const {
283 return static_cast<AtomicOrdering>(AtomicInfo.Ordering);
284 }
285
286 /// For cmpxchg atomic operations, return the atomic ordering requirements
287 /// when store does not occur.
288 AtomicOrdering getFailureOrdering() const {
289 return static_cast<AtomicOrdering>(AtomicInfo.FailureOrdering);
290 }
291
292 /// Return a single atomic ordering that is at least as strong as both the
293 /// success and failure orderings for an atomic operation. (For operations
294 /// other than cmpxchg, this is equivalent to getSuccessOrdering().)
295 AtomicOrdering getMergedOrdering() const {
296 return getMergedAtomicOrdering(AO: getSuccessOrdering(), Other: getFailureOrdering());
297 }
298
299 bool isLoad() const { return FlagVals & MOLoad; }
300 bool isStore() const { return FlagVals & MOStore; }
301 bool isVolatile() const { return FlagVals & MOVolatile; }
302 bool isNonTemporal() const { return FlagVals & MONonTemporal; }
303 bool isDereferenceable() const { return FlagVals & MODereferenceable; }
304 bool isInvariant() const { return FlagVals & MOInvariant; }
305
306 /// Returns true if this operation has an atomic ordering requirement of
307 /// unordered or higher, false otherwise.
308 bool isAtomic() const {
309 return getSuccessOrdering() != AtomicOrdering::NotAtomic;
310 }
311
312 /// Returns true if this memory operation doesn't have any ordering
313 /// constraints other than normal aliasing. Volatile and (ordered) atomic
314 /// memory operations can't be reordered.
315 bool isUnordered() const {
316 return (getSuccessOrdering() == AtomicOrdering::NotAtomic ||
317 getSuccessOrdering() == AtomicOrdering::Unordered) &&
318 !isVolatile();
319 }
320
321 /// Update this MachineMemOperand to reflect the alignment of MMO, if it has a
322 /// greater alignment. This must only be used when the new alignment applies
323 /// to all users of this MachineMemOperand.
324 LLVM_ABI void refineAlignment(const MachineMemOperand *MMO);
325
326 /// Change the SourceValue for this MachineMemOperand. This should only be
327 /// used when an object is being relocated and all references to it are being
328 /// updated.
329 void setValue(const Value *NewSV) { PtrInfo.V = NewSV; }
330 void setValue(const PseudoSourceValue *NewSV) { PtrInfo.V = NewSV; }
331 void setOffset(int64_t NewOffset) { PtrInfo.Offset = NewOffset; }
332
333 /// Reset the tracked memory type.
334 void setType(LLT NewTy) {
335 MemoryType = NewTy;
336 }
337
338 /// Unset the tracked range metadata.
339 void clearRanges() { Ranges = nullptr; }
340
341 /// Support for operator<<.
342 /// @{
343 LLVM_ABI void print(raw_ostream &OS, ModuleSlotTracker &MST,
344 SmallVectorImpl<StringRef> &SSNs,
345 const LLVMContext &Context, const MachineFrameInfo *MFI,
346 const TargetInstrInfo *TII) const;
347 /// @}
348
349 friend bool operator==(const MachineMemOperand &LHS,
350 const MachineMemOperand &RHS) {
351 return LHS.getValue() == RHS.getValue() &&
352 LHS.getPseudoValue() == RHS.getPseudoValue() &&
353 LHS.getSize() == RHS.getSize() &&
354 LHS.getOffset() == RHS.getOffset() &&
355 LHS.getFlags() == RHS.getFlags() &&
356 LHS.getAAInfo() == RHS.getAAInfo() &&
357 LHS.getRanges() == RHS.getRanges() &&
358 LHS.getAlign() == RHS.getAlign() &&
359 LHS.getAddrSpace() == RHS.getAddrSpace();
360 }
361
362 friend bool operator!=(const MachineMemOperand &LHS,
363 const MachineMemOperand &RHS) {
364 return !(LHS == RHS);
365 }
366};
367
368} // End llvm namespace
369
370#endif
371

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source code of llvm/include/llvm/CodeGen/MachineMemOperand.h