1//===-- IR/VPIntrinsics.def - Describes llvm.vp.* Intrinsics -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains descriptions of the various Vector Predication intrinsics.
10// This is used as a central place for enumerating the different instructions
11// and should eventually be the place to put comments about the instructions.
12//
13//===----------------------------------------------------------------------===//
14
15// NOTE: NO INCLUDE GUARD DESIRED!
16
17// Provide definitions of macros so that users of this file do not have to
18// define everything to use it...
19//
20// Register a VP intrinsic and begin its property scope.
21// All VP intrinsic scopes are top level, ie it is illegal to place a
22// BEGIN_REGISTER_VP_INTRINSIC within a VP intrinsic scope.
23// \p VPID The VP intrinsic id.
24// \p MASKPOS The mask operand position.
25// \p EVLPOS The explicit vector length operand position.
26#ifndef BEGIN_REGISTER_VP_INTRINSIC
27#define BEGIN_REGISTER_VP_INTRINSIC(VPID, MASKPOS, EVLPOS)
28#endif
29
30// End the property scope of a VP intrinsic.
31#ifndef END_REGISTER_VP_INTRINSIC
32#define END_REGISTER_VP_INTRINSIC(VPID)
33#endif
34
35// Register a new VP SDNode and begin its property scope.
36// When the SDNode scope is nested within a VP intrinsic scope, it is
37// implicitly registered as the canonical SDNode for this VP intrinsic. There
38// is one VP intrinsic that maps directly to one SDNode that goes by the
39// same name. Since the operands are also the same, we open the property
40// scopes for both the VPIntrinsic and the SDNode at once.
41// \p VPSD The SelectionDAG Node id (eg VP_ADD).
42// \p LEGALPOS The operand position of the SDNode that is used for legalizing.
43// If LEGALPOS < 0, then the return type given by
44// TheNode->getValueType(-1-LEGALPOS) is used.
45// \p TDNAME The name of the TableGen definition of this SDNode.
46// \p MASKPOS The mask operand position.
47// \p EVLPOS The explicit vector length operand position.
48#ifndef BEGIN_REGISTER_VP_SDNODE
49#define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, EVLPOS)
50#endif
51
52// End the property scope of a new VP SDNode.
53#ifndef END_REGISTER_VP_SDNODE
54#define END_REGISTER_VP_SDNODE(VPSD)
55#endif
56
57// Helper macro to set up the mapping from VP intrinsic to ISD opcode.
58// Note: More than one VP intrinsic may map to one ISD opcode.
59#ifndef HELPER_MAP_VPID_TO_VPSD
60#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD)
61#endif
62
63// Helper macros for the common "1:1 - Intrinsic : SDNode" case.
64//
65// There is one VP intrinsic that maps directly to one SDNode that goes by the
66// same name. Since the operands are also the same, we open the property
67// scopes for both the VPIntrinsic and the SDNode at once.
68//
69// \p VPID The canonical name (eg `vp_add`, which at the same time is the
70// name of the intrinsic and the TableGen def of the SDNode).
71// \p MASKPOS The mask operand position.
72// \p EVLPOS The explicit vector length operand position.
73// \p VPSD The SelectionDAG Node id (eg VP_ADD).
74// \p LEGALPOS The operand position of the SDNode that is used for legalizing
75// this SDNode. This can be `-1`, in which case the return type of
76// the SDNode is used.
77#define BEGIN_REGISTER_VP(VPID, MASKPOS, EVLPOS, VPSD, LEGALPOS) \
78 BEGIN_REGISTER_VP_INTRINSIC(VPID, MASKPOS, EVLPOS) \
79 BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, VPID, MASKPOS, EVLPOS) \
80 HELPER_MAP_VPID_TO_VPSD(VPID, VPSD)
81
82#define END_REGISTER_VP(VPID, VPSD) \
83 END_REGISTER_VP_INTRINSIC(VPID) \
84 END_REGISTER_VP_SDNODE(VPSD)
85
86// The following macros attach properties to the scope they are placed in. This
87// assigns the property to the VP Intrinsic and/or SDNode that belongs to the
88// scope.
89//
90// Property Macros {
91
92// The intrinsic and/or SDNode has the same function as this LLVM IR Opcode.
93// \p OPC The opcode of the instruction with the same function.
94#ifndef VP_PROPERTY_FUNCTIONAL_OPC
95#define VP_PROPERTY_FUNCTIONAL_OPC(OPC)
96#endif
97
98// Whether the intrinsic may have a rounding mode or exception behavior operand
99// bundle.
100// \p HASROUND '1' if the intrinsic can have a rounding mode operand bundle,
101// '0' otherwise.
102// \p HASEXCEPT '1' if the intrinsic can have an exception behavior operand
103// bundle, '0' otherwise.
104// \p INTRINID The constrained fp intrinsic this VP intrinsic corresponds to.
105#ifndef VP_PROPERTY_CONSTRAINEDFP
106#define VP_PROPERTY_CONSTRAINEDFP(HASROUND, HASEXCEPT, INTRINID)
107#endif
108
109// The intrinsic and/or SDNode has the same function as this ISD Opcode.
110// \p SDOPC The opcode of the instruction with the same function.
111#ifndef VP_PROPERTY_FUNCTIONAL_SDOPC
112#define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC)
113#endif
114
115// Map this VP intrinsic to its canonical functional intrinsic.
116// \p INTRIN The non-VP intrinsics with the same function.
117#ifndef VP_PROPERTY_FUNCTIONAL_INTRINSIC
118#define VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN)
119#endif
120
121// This VP Intrinsic has no functionally-equivalent non-VP opcode or intrinsic.
122#ifndef VP_PROPERTY_NO_FUNCTIONAL
123#define VP_PROPERTY_NO_FUNCTIONAL
124#endif
125
126// This VP Intrinsic is a memory operation
127// The pointer arg is at POINTERPOS and the data arg is at DATAPOS.
128#ifndef VP_PROPERTY_MEMOP
129#define VP_PROPERTY_MEMOP(POINTERPOS, DATAPOS)
130#endif
131
132// Map this VP reduction intrinsic to its reduction operand positions.
133#ifndef VP_PROPERTY_REDUCTION
134#define VP_PROPERTY_REDUCTION(STARTPOS, VECTORPOS)
135#endif
136
137// A property to infer VP binary-op SDNode opcodes automatically.
138#ifndef VP_PROPERTY_BINARYOP
139#define VP_PROPERTY_BINARYOP
140#endif
141
142// A property to infer VP type casts automatically.
143#ifndef VP_PROPERTY_CASTOP
144#define VP_PROPERTY_CASTOP
145#endif
146
147// This VP Intrinsic is a comparison operation
148// The condition code arg is at CCPOS and accepts floating-point condition
149// codes if ISFP is set, else it accepts integer condition codes.
150#ifndef VP_PROPERTY_CMP
151#define VP_PROPERTY_CMP(CCPOS, ISFP)
152#endif
153
154/// } Property Macros
155
156///// Integer Arithmetic {
157
158// Specialized helper macro for integer binary operators (%x, %y, %mask, %evl).
159#ifdef HELPER_REGISTER_BINARY_INT_VP
160#error \
161 "The internal helper macro HELPER_REGISTER_BINARY_INT_VP is already defined!"
162#endif
163#define HELPER_REGISTER_BINARY_INT_VP(VPID, VPSD, IROPC, SDOPC) \
164 BEGIN_REGISTER_VP(VPID, 2, 3, VPSD, -1) \
165 VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \
166 VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
167 VP_PROPERTY_BINARYOP \
168 END_REGISTER_VP(VPID, VPSD)
169
170// llvm.vp.add(x,y,mask,vlen)
171HELPER_REGISTER_BINARY_INT_VP(vp_add, VP_ADD, Add, ADD)
172
173// llvm.vp.and(x,y,mask,vlen)
174HELPER_REGISTER_BINARY_INT_VP(vp_and, VP_AND, And, AND)
175
176// llvm.vp.ashr(x,y,mask,vlen)
177HELPER_REGISTER_BINARY_INT_VP(vp_ashr, VP_ASHR, AShr, SRA)
178
179// llvm.vp.lshr(x,y,mask,vlen)
180HELPER_REGISTER_BINARY_INT_VP(vp_lshr, VP_LSHR, LShr, SRL)
181
182// llvm.vp.mul(x,y,mask,vlen)
183HELPER_REGISTER_BINARY_INT_VP(vp_mul, VP_MUL, Mul, MUL)
184
185// llvm.vp.or(x,y,mask,vlen)
186HELPER_REGISTER_BINARY_INT_VP(vp_or, VP_OR, Or, OR)
187
188// llvm.vp.sdiv(x,y,mask,vlen)
189HELPER_REGISTER_BINARY_INT_VP(vp_sdiv, VP_SDIV, SDiv, SDIV)
190
191// llvm.vp.shl(x,y,mask,vlen)
192HELPER_REGISTER_BINARY_INT_VP(vp_shl, VP_SHL, Shl, SHL)
193
194// llvm.vp.srem(x,y,mask,vlen)
195HELPER_REGISTER_BINARY_INT_VP(vp_srem, VP_SREM, SRem, SREM)
196
197// llvm.vp.sub(x,y,mask,vlen)
198HELPER_REGISTER_BINARY_INT_VP(vp_sub, VP_SUB, Sub, SUB)
199
200// llvm.vp.udiv(x,y,mask,vlen)
201HELPER_REGISTER_BINARY_INT_VP(vp_udiv, VP_UDIV, UDiv, UDIV)
202
203// llvm.vp.urem(x,y,mask,vlen)
204HELPER_REGISTER_BINARY_INT_VP(vp_urem, VP_UREM, URem, UREM)
205
206// llvm.vp.xor(x,y,mask,vlen)
207HELPER_REGISTER_BINARY_INT_VP(vp_xor, VP_XOR, Xor, XOR)
208
209#undef HELPER_REGISTER_BINARY_INT_VP
210
211// llvm.vp.smin(x,y,mask,vlen)
212BEGIN_REGISTER_VP(vp_smin, 2, 3, VP_SMIN, -1)
213VP_PROPERTY_BINARYOP
214VP_PROPERTY_FUNCTIONAL_SDOPC(SMIN)
215VP_PROPERTY_FUNCTIONAL_INTRINSIC(smin)
216END_REGISTER_VP(vp_smin, VP_SMIN)
217
218// llvm.vp.smax(x,y,mask,vlen)
219BEGIN_REGISTER_VP(vp_smax, 2, 3, VP_SMAX, -1)
220VP_PROPERTY_BINARYOP
221VP_PROPERTY_FUNCTIONAL_SDOPC(SMAX)
222VP_PROPERTY_FUNCTIONAL_INTRINSIC(smax)
223END_REGISTER_VP(vp_smax, VP_SMAX)
224
225// llvm.vp.umin(x,y,mask,vlen)
226BEGIN_REGISTER_VP(vp_umin, 2, 3, VP_UMIN, -1)
227VP_PROPERTY_BINARYOP
228VP_PROPERTY_FUNCTIONAL_SDOPC(UMIN)
229VP_PROPERTY_FUNCTIONAL_INTRINSIC(umin)
230END_REGISTER_VP(vp_umin, VP_UMIN)
231
232// llvm.vp.umax(x,y,mask,vlen)
233BEGIN_REGISTER_VP(vp_umax, 2, 3, VP_UMAX, -1)
234VP_PROPERTY_BINARYOP
235VP_PROPERTY_FUNCTIONAL_SDOPC(UMAX)
236VP_PROPERTY_FUNCTIONAL_INTRINSIC(umax)
237END_REGISTER_VP(vp_umax, VP_UMAX)
238
239// llvm.vp.abs(x,is_int_min_poison,mask,vlen)
240BEGIN_REGISTER_VP_INTRINSIC(vp_abs, 2, 3)
241BEGIN_REGISTER_VP_SDNODE(VP_ABS, -1, vp_abs, 1, 2)
242HELPER_MAP_VPID_TO_VPSD(vp_abs, VP_ABS)
243VP_PROPERTY_FUNCTIONAL_INTRINSIC(abs)
244VP_PROPERTY_FUNCTIONAL_SDOPC(ABS)
245END_REGISTER_VP(vp_abs, VP_ABS)
246
247// llvm.vp.bswap(x,mask,vlen)
248BEGIN_REGISTER_VP(vp_bswap, 1, 2, VP_BSWAP, -1)
249VP_PROPERTY_FUNCTIONAL_INTRINSIC(bswap)
250VP_PROPERTY_FUNCTIONAL_SDOPC(BSWAP)
251END_REGISTER_VP(vp_bswap, VP_BSWAP)
252
253// llvm.vp.bitreverse(x,mask,vlen)
254BEGIN_REGISTER_VP(vp_bitreverse, 1, 2, VP_BITREVERSE, -1)
255VP_PROPERTY_FUNCTIONAL_INTRINSIC(bitreverse)
256VP_PROPERTY_FUNCTIONAL_SDOPC(BITREVERSE)
257END_REGISTER_VP(vp_bitreverse, VP_BITREVERSE)
258
259// llvm.vp.ctpop(x,mask,vlen)
260BEGIN_REGISTER_VP(vp_ctpop, 1, 2, VP_CTPOP, -1)
261VP_PROPERTY_FUNCTIONAL_INTRINSIC(ctpop)
262VP_PROPERTY_FUNCTIONAL_SDOPC(CTPOP)
263END_REGISTER_VP(vp_ctpop, VP_CTPOP)
264
265// llvm.vp.ctlz(x,is_zero_poison,mask,vlen)
266BEGIN_REGISTER_VP_INTRINSIC(vp_ctlz, 2, 3)
267BEGIN_REGISTER_VP_SDNODE(VP_CTLZ, -1, vp_ctlz, 1, 2)
268VP_PROPERTY_FUNCTIONAL_INTRINSIC(ctlz)
269VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ)
270END_REGISTER_VP_SDNODE(VP_CTLZ)
271BEGIN_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF, -1, vp_ctlz_zero_undef, 1, 2)
272END_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF)
273END_REGISTER_VP_INTRINSIC(vp_ctlz)
274
275// llvm.vp.cttz(x,is_zero_poison,mask,vlen)
276BEGIN_REGISTER_VP_INTRINSIC(vp_cttz, 2, 3)
277BEGIN_REGISTER_VP_SDNODE(VP_CTTZ, -1, vp_cttz, 1, 2)
278VP_PROPERTY_FUNCTIONAL_INTRINSIC(cttz)
279VP_PROPERTY_FUNCTIONAL_SDOPC(CTTZ)
280END_REGISTER_VP_SDNODE(VP_CTTZ)
281BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_UNDEF, -1, vp_cttz_zero_undef, 1, 2)
282END_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_UNDEF)
283END_REGISTER_VP_INTRINSIC(vp_cttz)
284
285// llvm.vp.fshl(x,y,z,mask,vlen)
286BEGIN_REGISTER_VP(vp_fshl, 3, 4, VP_FSHL, -1)
287VP_PROPERTY_FUNCTIONAL_INTRINSIC(fshl)
288VP_PROPERTY_FUNCTIONAL_SDOPC(FSHL)
289END_REGISTER_VP(vp_fshl, VP_FSHL)
290
291// llvm.vp.fshr(x,y,z,mask,vlen)
292BEGIN_REGISTER_VP(vp_fshr, 3, 4, VP_FSHR, -1)
293VP_PROPERTY_FUNCTIONAL_INTRINSIC(fshr)
294VP_PROPERTY_FUNCTIONAL_SDOPC(FSHR)
295END_REGISTER_VP(vp_fshr, VP_FSHR)
296
297// llvm.vp.sadd.sat(x,y,mask,vlen)
298BEGIN_REGISTER_VP(vp_sadd_sat, 2, 3, VP_SADDSAT, -1)
299VP_PROPERTY_FUNCTIONAL_INTRINSIC(sadd_sat)
300VP_PROPERTY_FUNCTIONAL_SDOPC(SADDSAT)
301END_REGISTER_VP(vp_sadd_sat, VP_SADDSAT)
302
303// llvm.vp.uadd.sat(x,y,mask,vlen)
304BEGIN_REGISTER_VP(vp_uadd_sat, 2, 3, VP_UADDSAT, -1)
305VP_PROPERTY_FUNCTIONAL_INTRINSIC(uadd_sat)
306VP_PROPERTY_FUNCTIONAL_SDOPC(UADDSAT)
307END_REGISTER_VP(vp_uadd_sat, VP_UADDSAT)
308
309// llvm.vp.ssub.sat(x,y,mask,vlen)
310BEGIN_REGISTER_VP(vp_ssub_sat, 2, 3, VP_SSUBSAT, -1)
311VP_PROPERTY_FUNCTIONAL_INTRINSIC(ssub_sat)
312VP_PROPERTY_FUNCTIONAL_SDOPC(SSUBSAT)
313END_REGISTER_VP(vp_ssub_sat, VP_SSUBSAT)
314
315// llvm.vp.usub.sat(x,y,mask,vlen)
316BEGIN_REGISTER_VP(vp_usub_sat, 2, 3, VP_USUBSAT, -1)
317VP_PROPERTY_FUNCTIONAL_INTRINSIC(usub_sat)
318VP_PROPERTY_FUNCTIONAL_SDOPC(USUBSAT)
319END_REGISTER_VP(vp_usub_sat, VP_USUBSAT)
320///// } Integer Arithmetic
321
322///// Floating-Point Arithmetic {
323
324// Specialized helper macro for floating-point binary operators
325// <operation>(%x, %y, %mask, %evl).
326#ifdef HELPER_REGISTER_BINARY_FP_VP
327#error \
328 "The internal helper macro HELPER_REGISTER_BINARY_FP_VP is already defined!"
329#endif
330#define HELPER_REGISTER_BINARY_FP_VP(OPSUFFIX, VPSD, IROPC, SDOPC) \
331 BEGIN_REGISTER_VP(vp_##OPSUFFIX, 2, 3, VPSD, -1) \
332 VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \
333 VP_PROPERTY_CONSTRAINEDFP(1, 1, experimental_constrained_##OPSUFFIX) \
334 VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
335 VP_PROPERTY_BINARYOP \
336 END_REGISTER_VP(vp_##OPSUFFIX, VPSD)
337
338// llvm.vp.fadd(x,y,mask,vlen)
339HELPER_REGISTER_BINARY_FP_VP(fadd, VP_FADD, FAdd, FADD)
340
341// llvm.vp.fsub(x,y,mask,vlen)
342HELPER_REGISTER_BINARY_FP_VP(fsub, VP_FSUB, FSub, FSUB)
343
344// llvm.vp.fmul(x,y,mask,vlen)
345HELPER_REGISTER_BINARY_FP_VP(fmul, VP_FMUL, FMul, FMUL)
346
347// llvm.vp.fdiv(x,y,mask,vlen)
348HELPER_REGISTER_BINARY_FP_VP(fdiv, VP_FDIV, FDiv, FDIV)
349
350// llvm.vp.frem(x,y,mask,vlen)
351HELPER_REGISTER_BINARY_FP_VP(frem, VP_FREM, FRem, FREM)
352
353#undef HELPER_REGISTER_BINARY_FP_VP
354
355// llvm.vp.fneg(x,mask,vlen)
356BEGIN_REGISTER_VP(vp_fneg, 1, 2, VP_FNEG, -1)
357VP_PROPERTY_FUNCTIONAL_OPC(FNeg)
358VP_PROPERTY_FUNCTIONAL_SDOPC(FNEG)
359END_REGISTER_VP(vp_fneg, VP_FNEG)
360
361// llvm.vp.fabs(x,mask,vlen)
362BEGIN_REGISTER_VP(vp_fabs, 1, 2, VP_FABS, -1)
363VP_PROPERTY_FUNCTIONAL_INTRINSIC(fabs)
364VP_PROPERTY_FUNCTIONAL_SDOPC(FABS)
365END_REGISTER_VP(vp_fabs, VP_FABS)
366
367// llvm.vp.sqrt(x,mask,vlen)
368BEGIN_REGISTER_VP(vp_sqrt, 1, 2, VP_SQRT, -1)
369VP_PROPERTY_FUNCTIONAL_INTRINSIC(sqrt)
370VP_PROPERTY_FUNCTIONAL_SDOPC(FSQRT)
371END_REGISTER_VP(vp_sqrt, VP_SQRT)
372
373// llvm.vp.fma(x,y,z,mask,vlen)
374BEGIN_REGISTER_VP(vp_fma, 3, 4, VP_FMA, -1)
375VP_PROPERTY_CONSTRAINEDFP(1, 1, experimental_constrained_fma)
376VP_PROPERTY_FUNCTIONAL_INTRINSIC(fma)
377VP_PROPERTY_FUNCTIONAL_SDOPC(FMA)
378END_REGISTER_VP(vp_fma, VP_FMA)
379
380// llvm.vp.fmuladd(x,y,z,mask,vlen)
381BEGIN_REGISTER_VP(vp_fmuladd, 3, 4, VP_FMULADD, -1)
382VP_PROPERTY_CONSTRAINEDFP(1, 1, experimental_constrained_fmuladd)
383VP_PROPERTY_FUNCTIONAL_INTRINSIC(fmuladd)
384VP_PROPERTY_FUNCTIONAL_SDOPC(FMAD)
385END_REGISTER_VP(vp_fmuladd, VP_FMULADD)
386
387// llvm.vp.copysign(x,y,mask,vlen)
388BEGIN_REGISTER_VP(vp_copysign, 2, 3, VP_FCOPYSIGN, -1)
389VP_PROPERTY_BINARYOP
390VP_PROPERTY_FUNCTIONAL_SDOPC(FCOPYSIGN)
391VP_PROPERTY_FUNCTIONAL_INTRINSIC(copysign)
392END_REGISTER_VP(vp_copysign, VP_FCOPYSIGN)
393
394// llvm.vp.minnum(x,y,mask,vlen)
395BEGIN_REGISTER_VP(vp_minnum, 2, 3, VP_FMINNUM, -1)
396VP_PROPERTY_BINARYOP
397VP_PROPERTY_FUNCTIONAL_SDOPC(FMINNUM)
398VP_PROPERTY_FUNCTIONAL_INTRINSIC(minnum)
399END_REGISTER_VP(vp_minnum, VP_FMINNUM)
400
401// llvm.vp.maxnum(x,y,mask,vlen)
402BEGIN_REGISTER_VP(vp_maxnum, 2, 3, VP_FMAXNUM, -1)
403VP_PROPERTY_BINARYOP
404VP_PROPERTY_FUNCTIONAL_SDOPC(FMAXNUM)
405VP_PROPERTY_FUNCTIONAL_INTRINSIC(maxnum)
406END_REGISTER_VP(vp_maxnum, VP_FMAXNUM)
407
408// llvm.vp.minimum(x,y,mask,vlen)
409BEGIN_REGISTER_VP(vp_minimum, 2, 3, VP_FMINIMUM, -1)
410VP_PROPERTY_BINARYOP
411VP_PROPERTY_FUNCTIONAL_SDOPC(FMINIMUM)
412VP_PROPERTY_FUNCTIONAL_INTRINSIC(minimum)
413END_REGISTER_VP(vp_minimum, VP_FMINIMUM)
414
415// llvm.vp.maximum(x,y,mask,vlen)
416BEGIN_REGISTER_VP(vp_maximum, 2, 3, VP_FMAXIMUM, -1)
417VP_PROPERTY_BINARYOP
418VP_PROPERTY_FUNCTIONAL_SDOPC(FMAXIMUM)
419VP_PROPERTY_FUNCTIONAL_INTRINSIC(maximum)
420END_REGISTER_VP(vp_maximum, VP_FMAXIMUM)
421
422// llvm.vp.ceil(x,mask,vlen)
423BEGIN_REGISTER_VP(vp_ceil, 1, 2, VP_FCEIL, -1)
424VP_PROPERTY_FUNCTIONAL_INTRINSIC(ceil)
425VP_PROPERTY_FUNCTIONAL_SDOPC(FCEIL)
426END_REGISTER_VP(vp_ceil, VP_FCEIL)
427
428// llvm.vp.floor(x,mask,vlen)
429BEGIN_REGISTER_VP(vp_floor, 1, 2, VP_FFLOOR, -1)
430VP_PROPERTY_FUNCTIONAL_INTRINSIC(floor)
431VP_PROPERTY_FUNCTIONAL_SDOPC(FFLOOR)
432END_REGISTER_VP(vp_floor, VP_FFLOOR)
433
434// llvm.vp.round(x,mask,vlen)
435BEGIN_REGISTER_VP(vp_round, 1, 2, VP_FROUND, -1)
436VP_PROPERTY_FUNCTIONAL_INTRINSIC(round)
437VP_PROPERTY_FUNCTIONAL_SDOPC(FROUND)
438END_REGISTER_VP(vp_round, VP_FROUND)
439
440// llvm.vp.roundeven(x,mask,vlen)
441BEGIN_REGISTER_VP(vp_roundeven, 1, 2, VP_FROUNDEVEN, -1)
442VP_PROPERTY_FUNCTIONAL_INTRINSIC(roundeven)
443VP_PROPERTY_FUNCTIONAL_SDOPC(FROUNDEVEN)
444END_REGISTER_VP(vp_roundeven, VP_FROUNDEVEN)
445
446// llvm.vp.roundtozero(x,mask,vlen)
447BEGIN_REGISTER_VP(vp_roundtozero, 1, 2, VP_FROUNDTOZERO, -1)
448VP_PROPERTY_FUNCTIONAL_INTRINSIC(trunc)
449VP_PROPERTY_FUNCTIONAL_SDOPC(FTRUNC)
450END_REGISTER_VP(vp_roundtozero, VP_FROUNDTOZERO)
451
452// llvm.vp.rint(x,mask,vlen)
453BEGIN_REGISTER_VP(vp_rint, 1, 2, VP_FRINT, -1)
454VP_PROPERTY_FUNCTIONAL_INTRINSIC(rint)
455VP_PROPERTY_FUNCTIONAL_SDOPC(FRINT)
456END_REGISTER_VP(vp_rint, VP_FRINT)
457
458// llvm.vp.nearbyint(x,mask,vlen)
459BEGIN_REGISTER_VP(vp_nearbyint, 1, 2, VP_FNEARBYINT, -1)
460VP_PROPERTY_FUNCTIONAL_INTRINSIC(nearbyint)
461VP_PROPERTY_FUNCTIONAL_SDOPC(FNEARBYINT)
462END_REGISTER_VP(vp_nearbyint, VP_FNEARBYINT)
463
464// llvm.vp.lrint(x,mask,vlen)
465BEGIN_REGISTER_VP(vp_lrint, 1, 2, VP_LRINT, 0)
466VP_PROPERTY_FUNCTIONAL_INTRINSIC(lrint)
467VP_PROPERTY_FUNCTIONAL_SDOPC(LRINT)
468END_REGISTER_VP(vp_lrint, VP_LRINT)
469
470// llvm.vp.llrint(x,mask,vlen)
471BEGIN_REGISTER_VP(vp_llrint, 1, 2, VP_LLRINT, 0)
472VP_PROPERTY_FUNCTIONAL_INTRINSIC(llrint)
473VP_PROPERTY_FUNCTIONAL_SDOPC(LLRINT)
474END_REGISTER_VP(vp_llrint, VP_LLRINT)
475
476///// } Floating-Point Arithmetic
477
478///// Type Casts {
479// Specialized helper macro for type conversions.
480// <operation>(%x, %mask, %evl).
481#ifdef HELPER_REGISTER_FP_CAST_VP
482#error \
483 "The internal helper macro HELPER_REGISTER_FP_CAST_VP is already defined!"
484#endif
485#define HELPER_REGISTER_FP_CAST_VP(OPSUFFIX, VPSD, IROPC, SDOPC, HASROUND) \
486 BEGIN_REGISTER_VP(vp_##OPSUFFIX, 1, 2, VPSD, -1) \
487 VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \
488 VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
489 VP_PROPERTY_CONSTRAINEDFP(HASROUND, 1, experimental_constrained_##OPSUFFIX) \
490 VP_PROPERTY_CASTOP \
491 END_REGISTER_VP(vp_##OPSUFFIX, VPSD)
492
493// llvm.vp.fptoui(x,mask,vlen)
494HELPER_REGISTER_FP_CAST_VP(fptoui, VP_FP_TO_UINT, FPToUI, FP_TO_UINT, 0)
495
496// llvm.vp.fptosi(x,mask,vlen)
497HELPER_REGISTER_FP_CAST_VP(fptosi, VP_FP_TO_SINT, FPToSI, FP_TO_SINT, 0)
498
499// llvm.vp.uitofp(x,mask,vlen)
500HELPER_REGISTER_FP_CAST_VP(uitofp, VP_UINT_TO_FP, UIToFP, UINT_TO_FP, 1)
501
502// llvm.vp.sitofp(x,mask,vlen)
503HELPER_REGISTER_FP_CAST_VP(sitofp, VP_SINT_TO_FP, SIToFP, SINT_TO_FP, 1)
504
505// llvm.vp.fptrunc(x,mask,vlen)
506HELPER_REGISTER_FP_CAST_VP(fptrunc, VP_FP_ROUND, FPTrunc, FP_ROUND, 1)
507
508// llvm.vp.fpext(x,mask,vlen)
509HELPER_REGISTER_FP_CAST_VP(fpext, VP_FP_EXTEND, FPExt, FP_EXTEND, 0)
510
511#undef HELPER_REGISTER_FP_CAST_VP
512
513// Specialized helper macro for integer type conversions.
514// <operation>(%x, %mask, %evl).
515#ifdef HELPER_REGISTER_INT_CAST_VP
516#error \
517 "The internal helper macro HELPER_REGISTER_INT_CAST_VP is already defined!"
518#endif
519#define HELPER_REGISTER_INT_CAST_VP(OPSUFFIX, VPSD, IROPC, SDOPC) \
520 BEGIN_REGISTER_VP(vp_##OPSUFFIX, 1, 2, VPSD, -1) \
521 VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \
522 VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
523 VP_PROPERTY_CASTOP \
524 END_REGISTER_VP(vp_##OPSUFFIX, VPSD)
525
526// llvm.vp.trunc(x,mask,vlen)
527HELPER_REGISTER_INT_CAST_VP(trunc, VP_TRUNCATE, Trunc, TRUNCATE)
528
529// llvm.vp.zext(x,mask,vlen)
530HELPER_REGISTER_INT_CAST_VP(zext, VP_ZERO_EXTEND, ZExt, ZERO_EXTEND)
531
532// llvm.vp.sext(x,mask,vlen)
533HELPER_REGISTER_INT_CAST_VP(sext, VP_SIGN_EXTEND, SExt, SIGN_EXTEND)
534
535// llvm.vp.ptrtoint(x,mask,vlen)
536BEGIN_REGISTER_VP(vp_ptrtoint, 1, 2, VP_PTRTOINT, -1)
537VP_PROPERTY_FUNCTIONAL_OPC(PtrToInt)
538VP_PROPERTY_CASTOP
539END_REGISTER_VP(vp_ptrtoint, VP_PTRTOINT)
540
541// llvm.vp.inttoptr(x,mask,vlen)
542BEGIN_REGISTER_VP(vp_inttoptr, 1, 2, VP_INTTOPTR, -1)
543VP_PROPERTY_FUNCTIONAL_OPC(IntToPtr)
544VP_PROPERTY_CASTOP
545END_REGISTER_VP(vp_inttoptr, VP_INTTOPTR)
546
547#undef HELPER_REGISTER_INT_CAST_VP
548
549///// } Type Casts
550
551///// Comparisons {
552
553// VP_SETCC (ISel only)
554BEGIN_REGISTER_VP_SDNODE(VP_SETCC, 0, vp_setcc, 3, 4)
555END_REGISTER_VP_SDNODE(VP_SETCC)
556
557// llvm.vp.fcmp(x,y,cc,mask,vlen)
558BEGIN_REGISTER_VP_INTRINSIC(vp_fcmp, 3, 4)
559HELPER_MAP_VPID_TO_VPSD(vp_fcmp, VP_SETCC)
560VP_PROPERTY_FUNCTIONAL_OPC(FCmp)
561VP_PROPERTY_CMP(2, true)
562VP_PROPERTY_CONSTRAINEDFP(0, 1, experimental_constrained_fcmp)
563END_REGISTER_VP_INTRINSIC(vp_fcmp)
564
565// llvm.vp.icmp(x,y,cc,mask,vlen)
566BEGIN_REGISTER_VP_INTRINSIC(vp_icmp, 3, 4)
567HELPER_MAP_VPID_TO_VPSD(vp_icmp, VP_SETCC)
568VP_PROPERTY_FUNCTIONAL_OPC(ICmp)
569VP_PROPERTY_CMP(2, false)
570END_REGISTER_VP_INTRINSIC(vp_icmp)
571
572///// } Comparisons
573
574// llvm.vp.is.fpclass(on_true,on_false,mask,vlen)
575BEGIN_REGISTER_VP(vp_is_fpclass, 2, 3, VP_IS_FPCLASS, 0)
576VP_PROPERTY_FUNCTIONAL_INTRINSIC(is_fpclass)
577END_REGISTER_VP(vp_is_fpclass, VP_IS_FPCLASS)
578
579///// Memory Operations {
580// llvm.vp.store(val,ptr,mask,vlen)
581BEGIN_REGISTER_VP_INTRINSIC(vp_store, 2, 3)
582// chain = VP_STORE chain,val,base,offset,mask,evl
583BEGIN_REGISTER_VP_SDNODE(VP_STORE, 1, vp_store, 4, 5)
584HELPER_MAP_VPID_TO_VPSD(vp_store, VP_STORE)
585VP_PROPERTY_FUNCTIONAL_OPC(Store)
586VP_PROPERTY_FUNCTIONAL_INTRINSIC(masked_store)
587VP_PROPERTY_MEMOP(1, 0)
588END_REGISTER_VP(vp_store, VP_STORE)
589
590// llvm.experimental.vp.strided.store(val,ptr,stride,mask,vlen)
591BEGIN_REGISTER_VP_INTRINSIC(experimental_vp_strided_store, 3, 4)
592// chain = EXPERIMENTAL_VP_STRIDED_STORE chain,val,base,offset,stride,mask,evl
593VP_PROPERTY_NO_FUNCTIONAL
594BEGIN_REGISTER_VP_SDNODE(EXPERIMENTAL_VP_STRIDED_STORE, 1, experimental_vp_strided_store, 5, 6)
595HELPER_MAP_VPID_TO_VPSD(experimental_vp_strided_store, EXPERIMENTAL_VP_STRIDED_STORE)
596VP_PROPERTY_MEMOP(1, 0)
597END_REGISTER_VP(experimental_vp_strided_store, EXPERIMENTAL_VP_STRIDED_STORE)
598
599// llvm.vp.scatter(ptr,val,mask,vlen)
600BEGIN_REGISTER_VP_INTRINSIC(vp_scatter, 2, 3)
601// chain = VP_SCATTER chain,val,base,indices,scale,mask,evl
602BEGIN_REGISTER_VP_SDNODE(VP_SCATTER, 1, vp_scatter, 5, 6)
603HELPER_MAP_VPID_TO_VPSD(vp_scatter, VP_SCATTER)
604VP_PROPERTY_FUNCTIONAL_INTRINSIC(masked_scatter)
605VP_PROPERTY_MEMOP(1, 0)
606END_REGISTER_VP(vp_scatter, VP_SCATTER)
607
608// llvm.vp.load(ptr,mask,vlen)
609BEGIN_REGISTER_VP_INTRINSIC(vp_load, 1, 2)
610// val,chain = VP_LOAD chain,base,offset,mask,evl
611BEGIN_REGISTER_VP_SDNODE(VP_LOAD, -1, vp_load, 3, 4)
612HELPER_MAP_VPID_TO_VPSD(vp_load, VP_LOAD)
613VP_PROPERTY_FUNCTIONAL_OPC(Load)
614VP_PROPERTY_FUNCTIONAL_INTRINSIC(masked_load)
615VP_PROPERTY_MEMOP(0, std::nullopt)
616END_REGISTER_VP(vp_load, VP_LOAD)
617
618// llvm.experimental.vp.strided.load(ptr,stride,mask,vlen)
619BEGIN_REGISTER_VP_INTRINSIC(experimental_vp_strided_load, 2, 3)
620// chain = EXPERIMENTAL_VP_STRIDED_LOAD chain,base,offset,stride,mask,evl
621VP_PROPERTY_NO_FUNCTIONAL
622BEGIN_REGISTER_VP_SDNODE(EXPERIMENTAL_VP_STRIDED_LOAD, -1, experimental_vp_strided_load, 4, 5)
623HELPER_MAP_VPID_TO_VPSD(experimental_vp_strided_load, EXPERIMENTAL_VP_STRIDED_LOAD)
624VP_PROPERTY_MEMOP(0, std::nullopt)
625END_REGISTER_VP(experimental_vp_strided_load, EXPERIMENTAL_VP_STRIDED_LOAD)
626
627// llvm.vp.gather(ptr,mask,vlen)
628BEGIN_REGISTER_VP_INTRINSIC(vp_gather, 1, 2)
629// val,chain = VP_GATHER chain,base,indices,scale,mask,evl
630BEGIN_REGISTER_VP_SDNODE(VP_GATHER, -1, vp_gather, 4, 5)
631HELPER_MAP_VPID_TO_VPSD(vp_gather, VP_GATHER)
632VP_PROPERTY_FUNCTIONAL_INTRINSIC(masked_gather)
633VP_PROPERTY_MEMOP(0, std::nullopt)
634END_REGISTER_VP(vp_gather, VP_GATHER)
635
636///// } Memory Operations
637
638///// Reductions {
639
640// Specialized helper macro for VP reductions (%start, %x, %mask, %evl).
641#ifdef HELPER_REGISTER_REDUCTION_VP
642#error \
643 "The internal helper macro HELPER_REGISTER_REDUCTION_VP is already defined!"
644#endif
645#define HELPER_REGISTER_REDUCTION_VP(VPID, VPSD, INTRIN) \
646 BEGIN_REGISTER_VP(VPID, 2, 3, VPSD, 1) \
647 VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) \
648 VP_PROPERTY_REDUCTION(0, 1) \
649 END_REGISTER_VP(VPID, VPSD)
650
651// llvm.vp.reduce.add(start,x,mask,vlen)
652HELPER_REGISTER_REDUCTION_VP(vp_reduce_add, VP_REDUCE_ADD,
653 vector_reduce_add)
654
655// llvm.vp.reduce.mul(start,x,mask,vlen)
656HELPER_REGISTER_REDUCTION_VP(vp_reduce_mul, VP_REDUCE_MUL,
657 vector_reduce_mul)
658
659// llvm.vp.reduce.and(start,x,mask,vlen)
660HELPER_REGISTER_REDUCTION_VP(vp_reduce_and, VP_REDUCE_AND,
661 vector_reduce_and)
662
663// llvm.vp.reduce.or(start,x,mask,vlen)
664HELPER_REGISTER_REDUCTION_VP(vp_reduce_or, VP_REDUCE_OR,
665 vector_reduce_or)
666
667// llvm.vp.reduce.xor(start,x,mask,vlen)
668HELPER_REGISTER_REDUCTION_VP(vp_reduce_xor, VP_REDUCE_XOR,
669 vector_reduce_xor)
670
671// llvm.vp.reduce.smax(start,x,mask,vlen)
672HELPER_REGISTER_REDUCTION_VP(vp_reduce_smax, VP_REDUCE_SMAX,
673 vector_reduce_smax)
674
675// llvm.vp.reduce.smin(start,x,mask,vlen)
676HELPER_REGISTER_REDUCTION_VP(vp_reduce_smin, VP_REDUCE_SMIN,
677 vector_reduce_smin)
678
679// llvm.vp.reduce.umax(start,x,mask,vlen)
680HELPER_REGISTER_REDUCTION_VP(vp_reduce_umax, VP_REDUCE_UMAX,
681 vector_reduce_umax)
682
683// llvm.vp.reduce.umin(start,x,mask,vlen)
684HELPER_REGISTER_REDUCTION_VP(vp_reduce_umin, VP_REDUCE_UMIN,
685 vector_reduce_umin)
686
687// llvm.vp.reduce.fmax(start,x,mask,vlen)
688HELPER_REGISTER_REDUCTION_VP(vp_reduce_fmax, VP_REDUCE_FMAX,
689 vector_reduce_fmax)
690
691// llvm.vp.reduce.fmin(start,x,mask,vlen)
692HELPER_REGISTER_REDUCTION_VP(vp_reduce_fmin, VP_REDUCE_FMIN,
693 vector_reduce_fmin)
694
695#undef HELPER_REGISTER_REDUCTION_VP
696
697// Specialized helper macro for VP reductions as above but with two forms:
698// sequential and reassociative. These manifest as the presence of 'reassoc'
699// fast-math flags in the IR and as two distinct ISD opcodes in the
700// SelectionDAG.
701// Note we by default map from the VP intrinsic to the SEQ ISD opcode, which
702// can then be relaxed to the non-SEQ ISD opcode if the 'reassoc' flag is set.
703#ifdef HELPER_REGISTER_REDUCTION_SEQ_VP
704#error \
705 "The internal helper macro HELPER_REGISTER_REDUCTION_SEQ_VP is already defined!"
706#endif
707#define HELPER_REGISTER_REDUCTION_SEQ_VP(VPID, VPSD, SEQ_VPSD, INTRIN) \
708 BEGIN_REGISTER_VP_INTRINSIC(VPID, 2, 3) \
709 BEGIN_REGISTER_VP_SDNODE(VPSD, 1, VPID, 2, 3) \
710 VP_PROPERTY_REDUCTION(0, 1) \
711 END_REGISTER_VP_SDNODE(VPSD) \
712 BEGIN_REGISTER_VP_SDNODE(SEQ_VPSD, 1, VPID, 2, 3) \
713 HELPER_MAP_VPID_TO_VPSD(VPID, SEQ_VPSD) \
714 VP_PROPERTY_REDUCTION(0, 1) \
715 END_REGISTER_VP_SDNODE(SEQ_VPSD) \
716 VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) \
717 END_REGISTER_VP_INTRINSIC(VPID)
718
719// llvm.vp.reduce.fadd(start,x,mask,vlen)
720HELPER_REGISTER_REDUCTION_SEQ_VP(vp_reduce_fadd, VP_REDUCE_FADD,
721 VP_REDUCE_SEQ_FADD,
722 vector_reduce_fadd)
723
724// llvm.vp.reduce.fmul(start,x,mask,vlen)
725HELPER_REGISTER_REDUCTION_SEQ_VP(vp_reduce_fmul, VP_REDUCE_FMUL,
726 VP_REDUCE_SEQ_FMUL,
727 vector_reduce_fmul)
728
729#undef HELPER_REGISTER_REDUCTION_SEQ_VP
730
731///// } Reduction
732
733///// Shuffles {
734
735// The mask 'cond' operand of llvm.vp.select and llvm.vp.merge are not reported
736// as masks with the BEGIN_REGISTER_VP_* macros. This is because, unlike other
737// VP intrinsics, these two have a defined result on lanes where the mask is
738// false.
739//
740// llvm.vp.select(cond,on_true,on_false,vlen)
741BEGIN_REGISTER_VP(vp_select, std::nullopt, 3, VP_SELECT, -1)
742VP_PROPERTY_FUNCTIONAL_OPC(Select)
743VP_PROPERTY_FUNCTIONAL_SDOPC(VSELECT)
744END_REGISTER_VP(vp_select, VP_SELECT)
745
746// llvm.vp.merge(cond,on_true,on_false,pivot)
747BEGIN_REGISTER_VP(vp_merge, std::nullopt, 3, VP_MERGE, -1)
748VP_PROPERTY_NO_FUNCTIONAL
749END_REGISTER_VP(vp_merge, VP_MERGE)
750
751BEGIN_REGISTER_VP(experimental_vp_splice, 3, 5, EXPERIMENTAL_VP_SPLICE, -1)
752VP_PROPERTY_NO_FUNCTIONAL
753END_REGISTER_VP(experimental_vp_splice, EXPERIMENTAL_VP_SPLICE)
754
755// llvm.experimental.vp.reverse(x,mask,vlen)
756BEGIN_REGISTER_VP(experimental_vp_reverse, 1, 2,
757 EXPERIMENTAL_VP_REVERSE, -1)
758VP_PROPERTY_NO_FUNCTIONAL
759END_REGISTER_VP(experimental_vp_reverse, EXPERIMENTAL_VP_REVERSE)
760
761///// } Shuffles
762
763#undef BEGIN_REGISTER_VP
764#undef BEGIN_REGISTER_VP_INTRINSIC
765#undef BEGIN_REGISTER_VP_SDNODE
766#undef END_REGISTER_VP
767#undef END_REGISTER_VP_INTRINSIC
768#undef END_REGISTER_VP_SDNODE
769#undef HELPER_MAP_VPID_TO_VPSD
770#undef VP_PROPERTY_BINARYOP
771#undef VP_PROPERTY_CASTOP
772#undef VP_PROPERTY_CMP
773#undef VP_PROPERTY_CONSTRAINEDFP
774#undef VP_PROPERTY_FUNCTIONAL_INTRINSIC
775#undef VP_PROPERTY_FUNCTIONAL_OPC
776#undef VP_PROPERTY_FUNCTIONAL_SDOPC
777#undef VP_PROPERTY_NO_FUNCTIONAL
778#undef VP_PROPERTY_MEMOP
779#undef VP_PROPERTY_REDUCTION
780

source code of llvm/include/llvm/IR/VPIntrinsics.def