1 | //===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file defines the target independent instruction opcodes. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | // NOTE: NO INCLUDE GUARD DESIRED! |
14 | |
15 | /// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. |
16 | /// |
17 | #ifndef HANDLE_TARGET_OPCODE |
18 | #define HANDLE_TARGET_OPCODE(OPC, NUM) |
19 | #endif |
20 | |
21 | /// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. |
22 | /// |
23 | #ifndef HANDLE_TARGET_OPCODE_MARKER |
24 | #define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) |
25 | #endif |
26 | |
27 | /// Every instruction defined here must also appear in Target.td. |
28 | /// |
29 | HANDLE_TARGET_OPCODE(PHI) |
30 | HANDLE_TARGET_OPCODE(INLINEASM) |
31 | HANDLE_TARGET_OPCODE(INLINEASM_BR) |
32 | HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) |
33 | HANDLE_TARGET_OPCODE(EH_LABEL) |
34 | HANDLE_TARGET_OPCODE(GC_LABEL) |
35 | HANDLE_TARGET_OPCODE(ANNOTATION_LABEL) |
36 | |
37 | /// KILL - This instruction is a noop that is used only to adjust the |
38 | /// liveness of registers. This can be useful when dealing with |
39 | /// sub-registers. |
40 | HANDLE_TARGET_OPCODE(KILL) |
41 | |
42 | /// EXTRACT_SUBREG - This instruction takes two operands: a register |
43 | /// that has subregisters, and a subregister index. It returns the |
44 | /// extracted subregister value. This is commonly used to implement |
45 | /// truncation operations on target architectures which support it. |
46 | HANDLE_TARGET_OPCODE() |
47 | |
48 | /// INSERT_SUBREG - This instruction takes three operands: a register that |
49 | /// has subregisters, a register providing an insert value, and a |
50 | /// subregister index. It returns the value of the first register with the |
51 | /// value of the second register inserted. The first register is often |
52 | /// defined by an IMPLICIT_DEF, because it is commonly used to implement |
53 | /// anyext operations on target architectures which support it. |
54 | HANDLE_TARGET_OPCODE(INSERT_SUBREG) |
55 | |
56 | /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. |
57 | HANDLE_TARGET_OPCODE(IMPLICIT_DEF) |
58 | |
59 | /// SUBREG_TO_REG - Assert the value of bits in a super register. |
60 | /// The result of this instruction is the value of the second operand inserted |
61 | /// into the subregister specified by the third operand. All other bits are |
62 | /// assumed to be equal to the bits in the immediate integer constant in the |
63 | /// first operand. This instruction just communicates information; No code |
64 | /// should be generated. |
65 | /// This is typically used after an instruction where the write to a subregister |
66 | /// implicitly cleared the bits in the super registers. |
67 | HANDLE_TARGET_OPCODE(SUBREG_TO_REG) |
68 | |
69 | /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain |
70 | /// register-to-register copy into a specific register class. This is only |
71 | /// used between instruction selection and MachineInstr creation, before |
72 | /// virtual registers have been created for all the instructions, and it's |
73 | /// only needed in cases where the register classes implied by the |
74 | /// instructions are insufficient. It is emitted as a COPY MachineInstr. |
75 | HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) |
76 | |
77 | /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic |
78 | HANDLE_TARGET_OPCODE(DBG_VALUE) |
79 | |
80 | /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic with a variadic |
81 | /// list of locations |
82 | HANDLE_TARGET_OPCODE(DBG_VALUE_LIST) |
83 | |
84 | /// DBG_INSTR_REF - A mapping of llvm.dbg.value referring to the instruction |
85 | /// that defines the value, rather than a virtual register. |
86 | HANDLE_TARGET_OPCODE(DBG_INSTR_REF) |
87 | |
88 | /// DBG_PHI - remainder of a PHI, identifies a program point where values |
89 | /// merge under control flow. |
90 | HANDLE_TARGET_OPCODE(DBG_PHI) |
91 | |
92 | /// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic |
93 | HANDLE_TARGET_OPCODE(DBG_LABEL) |
94 | |
95 | /// REG_SEQUENCE - This variadic instruction is used to form a register that |
96 | /// represents a consecutive sequence of sub-registers. It's used as a |
97 | /// register coalescing / allocation aid and must be eliminated before code |
98 | /// emission. |
99 | // In SDNode form, the first operand encodes the register class created by |
100 | // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index |
101 | // pair. Once it has been lowered to a MachineInstr, the regclass operand |
102 | // is no longer present. |
103 | /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 |
104 | /// After register coalescing references of v1024 should be replace with |
105 | /// v1027:3, v1025 with v1027:4, etc. |
106 | HANDLE_TARGET_OPCODE(REG_SEQUENCE) |
107 | |
108 | /// COPY - Target-independent register copy. This instruction can also be |
109 | /// used to copy between subregisters of virtual registers. |
110 | HANDLE_TARGET_OPCODE(COPY) |
111 | |
112 | /// BUNDLE - This instruction represents an instruction bundle. Instructions |
113 | /// which immediately follow a BUNDLE instruction which are marked with |
114 | /// 'InsideBundle' flag are inside the bundle. |
115 | HANDLE_TARGET_OPCODE(BUNDLE) |
116 | |
117 | /// Lifetime markers. |
118 | HANDLE_TARGET_OPCODE(LIFETIME_START) |
119 | HANDLE_TARGET_OPCODE(LIFETIME_END) |
120 | |
121 | /// Pseudo probe |
122 | HANDLE_TARGET_OPCODE(PSEUDO_PROBE) |
123 | |
124 | /// Arithmetic fence. |
125 | HANDLE_TARGET_OPCODE(ARITH_FENCE) |
126 | |
127 | /// A Stackmap instruction captures the location of live variables at its |
128 | /// position in the instruction stream. It is followed by a shadow of bytes |
129 | /// that must lie within the function and not contain another stackmap. |
130 | HANDLE_TARGET_OPCODE(STACKMAP) |
131 | |
132 | /// FEntry all - This is a marker instruction which gets translated into a raw fentry call. |
133 | HANDLE_TARGET_OPCODE(FENTRY_CALL) |
134 | |
135 | /// Patchable call instruction - this instruction represents a call to a |
136 | /// constant address, followed by a series of NOPs. It is intended to |
137 | /// support optimizations for dynamic languages (such as javascript) that |
138 | /// rewrite calls to runtimes with more efficient code sequences. |
139 | /// This also implies a stack map. |
140 | HANDLE_TARGET_OPCODE(PATCHPOINT) |
141 | |
142 | /// This pseudo-instruction loads the stack guard value. Targets which need |
143 | /// to prevent the stack guard value or address from being spilled to the |
144 | /// stack should override TargetLowering::emitLoadStackGuardNode and |
145 | /// additionally expand this pseudo after register allocation. |
146 | HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) |
147 | |
148 | /// These are used to support call sites that must have the stack adjusted |
149 | /// before the call (e.g. to initialize an argument passed by value). |
150 | /// See llvm.call.preallocated.{setup,arg} in the LangRef for more details. |
151 | HANDLE_TARGET_OPCODE(PREALLOCATED_SETUP) |
152 | HANDLE_TARGET_OPCODE(PREALLOCATED_ARG) |
153 | |
154 | /// Call instruction with associated vm state for deoptimization and list |
155 | /// of live pointers for relocation by the garbage collector. It is |
156 | /// intended to support garbage collection with fully precise relocating |
157 | /// collectors and deoptimizations in either the callee or caller. |
158 | HANDLE_TARGET_OPCODE(STATEPOINT) |
159 | |
160 | /// Instruction that records the offset of a local stack allocation passed to |
161 | /// llvm.localescape. It has two arguments: the symbol for the label and the |
162 | /// frame index of the local stack allocation. |
163 | HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) |
164 | |
165 | /// Wraps a machine instruction which can fault, bundled with associated |
166 | /// information on how to handle such a fault. |
167 | /// For example loading instruction that may page fault, bundled with associated |
168 | /// information on how to handle such a page fault. It is intended to support |
169 | /// "zero cost" null checks in managed languages by allowing LLVM to fold |
170 | /// comparisons into existing memory operations. |
171 | HANDLE_TARGET_OPCODE(FAULTING_OP) |
172 | |
173 | /// Precedes a machine instruction to add patchability constraints. An |
174 | /// instruction after PATCHABLE_OP has to either have a minimum |
175 | /// size or be preceded with a nop of that size. The first operand is |
176 | /// an immediate denoting the minimum size of the following instruction. |
177 | HANDLE_TARGET_OPCODE(PATCHABLE_OP) |
178 | |
179 | /// This is a marker instruction which gets translated into a nop sled, useful |
180 | /// for inserting instrumentation instructions at runtime. |
181 | HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) |
182 | |
183 | /// Wraps a return instruction and its operands to enable adding nop sleds |
184 | /// either before or after the return. The nop sleds are useful for inserting |
185 | /// instrumentation instructions at runtime. |
186 | /// The patch here replaces the return instruction. |
187 | HANDLE_TARGET_OPCODE(PATCHABLE_RET) |
188 | |
189 | /// This is a marker instruction which gets translated into a nop sled, useful |
190 | /// for inserting instrumentation instructions at runtime. |
191 | /// The patch here prepends the return instruction. |
192 | /// The same thing as in x86_64 is not possible for ARM because it has multiple |
193 | /// return instructions. Furthermore, CPU allows parametrized and even |
194 | /// conditional return instructions. In the current ARM implementation we are |
195 | /// making use of the fact that currently LLVM doesn't seem to generate |
196 | /// conditional return instructions. |
197 | /// On ARM, the same instruction can be used for popping multiple registers |
198 | /// from the stack and returning (it just pops pc register too), and LLVM |
199 | /// generates it sometimes. So we can't insert the sled between this stack |
200 | /// adjustment and the return without splitting the original instruction into 2 |
201 | /// instructions. So on ARM, rather than jumping into the exit trampoline, we |
202 | /// call it, it does the tracing, preserves the stack and returns. |
203 | HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) |
204 | |
205 | /// Wraps a tail call instruction and its operands to enable adding nop sleds |
206 | /// either before or after the tail exit. We use this as a disambiguation from |
207 | /// PATCHABLE_RET which specifically only works for return instructions. |
208 | HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) |
209 | |
210 | /// Wraps a logging call and its arguments with nop sleds. At runtime, this can |
211 | /// be patched to insert instrumentation instructions. |
212 | HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL) |
213 | |
214 | /// Wraps a typed logging call and its argument with nop sleds. At runtime, this |
215 | /// can be patched to insert instrumentation instructions. |
216 | HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL) |
217 | |
218 | HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL) |
219 | |
220 | // This is a fence with the singlethread scope. It represents a compiler memory |
221 | // barrier, but does not correspond to any generated instruction. |
222 | HANDLE_TARGET_OPCODE(MEMBARRIER) |
223 | |
224 | // Provides information about what jump table the following indirect branch is |
225 | // using. |
226 | HANDLE_TARGET_OPCODE(JUMP_TABLE_DEBUG_INFO) |
227 | |
228 | HANDLE_TARGET_OPCODE(CONVERGENCECTRL_ENTRY) |
229 | HANDLE_TARGET_OPCODE(CONVERGENCECTRL_ANCHOR) |
230 | HANDLE_TARGET_OPCODE(CONVERGENCECTRL_LOOP) |
231 | HANDLE_TARGET_OPCODE(CONVERGENCECTRL_GLUE) |
232 | |
233 | /// The following generic opcodes are not supposed to appear after ISel. |
234 | /// This is something we might want to relax, but for now, this is convenient |
235 | /// to produce diagnostics. |
236 | |
237 | /// Instructions which should not exist past instruction selection, but do not |
238 | /// generate code. These instructions only act as optimization hints. |
239 | HANDLE_TARGET_OPCODE(G_ASSERT_SEXT) |
240 | HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT) |
241 | HANDLE_TARGET_OPCODE(G_ASSERT_ALIGN) |
242 | HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START, |
243 | G_ASSERT_SEXT) |
244 | HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END, |
245 | G_ASSERT_ALIGN) |
246 | |
247 | /// Generic ADD instruction. This is an integer add. |
248 | HANDLE_TARGET_OPCODE(G_ADD) |
249 | HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) |
250 | |
251 | /// Generic SUB instruction. This is an integer sub. |
252 | HANDLE_TARGET_OPCODE(G_SUB) |
253 | |
254 | // Generic multiply instruction. |
255 | HANDLE_TARGET_OPCODE(G_MUL) |
256 | |
257 | // Generic signed division instruction. |
258 | HANDLE_TARGET_OPCODE(G_SDIV) |
259 | |
260 | // Generic unsigned division instruction. |
261 | HANDLE_TARGET_OPCODE(G_UDIV) |
262 | |
263 | // Generic signed remainder instruction. |
264 | HANDLE_TARGET_OPCODE(G_SREM) |
265 | |
266 | // Generic unsigned remainder instruction. |
267 | HANDLE_TARGET_OPCODE(G_UREM) |
268 | |
269 | // Generic signed divrem instruction. |
270 | HANDLE_TARGET_OPCODE(G_SDIVREM) |
271 | |
272 | // Generic unsigned divrem instruction. |
273 | HANDLE_TARGET_OPCODE(G_UDIVREM) |
274 | |
275 | /// Generic bitwise and instruction. |
276 | HANDLE_TARGET_OPCODE(G_AND) |
277 | |
278 | /// Generic bitwise or instruction. |
279 | HANDLE_TARGET_OPCODE(G_OR) |
280 | |
281 | /// Generic bitwise exclusive-or instruction. |
282 | HANDLE_TARGET_OPCODE(G_XOR) |
283 | |
284 | |
285 | HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF) |
286 | |
287 | /// Generic PHI instruction with types. |
288 | HANDLE_TARGET_OPCODE(G_PHI) |
289 | |
290 | /// Generic instruction to materialize the address of an alloca or other |
291 | /// stack-based object. |
292 | HANDLE_TARGET_OPCODE(G_FRAME_INDEX) |
293 | |
294 | /// Generic reference to global value. |
295 | HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) |
296 | |
297 | /// Generic instruction to materialize the address of an object in the constant |
298 | /// pool. |
299 | HANDLE_TARGET_OPCODE(G_CONSTANT_POOL) |
300 | |
301 | /// Generic instruction to extract blocks of bits from the register given |
302 | /// (typically a sub-register COPY after instruction selection). |
303 | HANDLE_TARGET_OPCODE() |
304 | |
305 | HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) |
306 | |
307 | /// Generic instruction to insert blocks of bits from the registers given into |
308 | /// the source. |
309 | HANDLE_TARGET_OPCODE(G_INSERT) |
310 | |
311 | /// Generic instruction to paste a variable number of components together into a |
312 | /// larger register. |
313 | HANDLE_TARGET_OPCODE(G_MERGE_VALUES) |
314 | |
315 | /// Generic instruction to create a vector value from a number of scalar |
316 | /// components. |
317 | HANDLE_TARGET_OPCODE(G_BUILD_VECTOR) |
318 | |
319 | /// Generic instruction to create a vector value from a number of scalar |
320 | /// components, which have types larger than the result vector elt type. |
321 | HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC) |
322 | |
323 | /// Generic instruction to create a vector by concatenating multiple vectors. |
324 | HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS) |
325 | |
326 | /// Generic pointer to int conversion. |
327 | HANDLE_TARGET_OPCODE(G_PTRTOINT) |
328 | |
329 | /// Generic int to pointer conversion. |
330 | HANDLE_TARGET_OPCODE(G_INTTOPTR) |
331 | |
332 | /// Generic bitcast. The source and destination types must be different, or a |
333 | /// COPY is the relevant instruction. |
334 | HANDLE_TARGET_OPCODE(G_BITCAST) |
335 | |
336 | /// Generic freeze. |
337 | HANDLE_TARGET_OPCODE(G_FREEZE) |
338 | |
339 | /// Constant folding barrier. |
340 | HANDLE_TARGET_OPCODE(G_CONSTANT_FOLD_BARRIER) |
341 | |
342 | // INTRINSIC fptrunc_round intrinsic. |
343 | HANDLE_TARGET_OPCODE(G_INTRINSIC_FPTRUNC_ROUND) |
344 | |
345 | /// INTRINSIC trunc intrinsic. |
346 | HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) |
347 | |
348 | /// INTRINSIC round intrinsic. |
349 | HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) |
350 | |
351 | /// INTRINSIC round to integer intrinsic. |
352 | HANDLE_TARGET_OPCODE(G_INTRINSIC_LRINT) |
353 | |
354 | /// INTRINSIC long round to integer intrinsic. |
355 | HANDLE_TARGET_OPCODE(G_INTRINSIC_LLRINT) |
356 | |
357 | /// INTRINSIC roundeven intrinsic. |
358 | HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUNDEVEN) |
359 | |
360 | /// INTRINSIC readcyclecounter |
361 | HANDLE_TARGET_OPCODE(G_READCYCLECOUNTER) |
362 | |
363 | /// INTRINSIC readsteadycounter |
364 | HANDLE_TARGET_OPCODE(G_READSTEADYCOUNTER) |
365 | |
366 | /// Generic load (including anyext load) |
367 | HANDLE_TARGET_OPCODE(G_LOAD) |
368 | |
369 | /// Generic signext load |
370 | HANDLE_TARGET_OPCODE(G_SEXTLOAD) |
371 | |
372 | /// Generic zeroext load |
373 | HANDLE_TARGET_OPCODE(G_ZEXTLOAD) |
374 | |
375 | /// Generic indexed load (including anyext load) |
376 | HANDLE_TARGET_OPCODE(G_INDEXED_LOAD) |
377 | |
378 | /// Generic indexed signext load |
379 | HANDLE_TARGET_OPCODE(G_INDEXED_SEXTLOAD) |
380 | |
381 | /// Generic indexed zeroext load |
382 | HANDLE_TARGET_OPCODE(G_INDEXED_ZEXTLOAD) |
383 | |
384 | /// Generic store. |
385 | HANDLE_TARGET_OPCODE(G_STORE) |
386 | |
387 | /// Generic indexed store. |
388 | HANDLE_TARGET_OPCODE(G_INDEXED_STORE) |
389 | |
390 | /// Generic atomic cmpxchg with internal success check. |
391 | HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS) |
392 | |
393 | /// Generic atomic cmpxchg. |
394 | HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG) |
395 | |
396 | /// Generic atomicrmw. |
397 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG) |
398 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD) |
399 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB) |
400 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND) |
401 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND) |
402 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR) |
403 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR) |
404 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX) |
405 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN) |
406 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX) |
407 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN) |
408 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_FADD) |
409 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB) |
410 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMAX) |
411 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMIN) |
412 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_UINC_WRAP) |
413 | HANDLE_TARGET_OPCODE(G_ATOMICRMW_UDEC_WRAP) |
414 | |
415 | // Marker for start of Generic AtomicRMW opcodes |
416 | HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_START, G_ATOMICRMW_XCHG) |
417 | |
418 | // Marker for end of Generic AtomicRMW opcodes |
419 | HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_END, G_ATOMICRMW_UDEC_WRAP) |
420 | |
421 | // Generic atomic fence |
422 | HANDLE_TARGET_OPCODE(G_FENCE) |
423 | |
424 | /// Generic prefetch |
425 | HANDLE_TARGET_OPCODE(G_PREFETCH) |
426 | |
427 | /// Generic conditional branch instruction. |
428 | HANDLE_TARGET_OPCODE(G_BRCOND) |
429 | |
430 | /// Generic indirect branch instruction. |
431 | HANDLE_TARGET_OPCODE(G_BRINDIRECT) |
432 | |
433 | /// Begin an invoke region marker. |
434 | HANDLE_TARGET_OPCODE(G_INVOKE_REGION_START) |
435 | |
436 | /// Generic intrinsic use (without side effects). |
437 | HANDLE_TARGET_OPCODE(G_INTRINSIC) |
438 | |
439 | /// Generic intrinsic use (with side effects). |
440 | HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) |
441 | |
442 | /// Generic intrinsic use (without side effects). |
443 | HANDLE_TARGET_OPCODE(G_INTRINSIC_CONVERGENT) |
444 | |
445 | /// Generic intrinsic use (with side effects). |
446 | HANDLE_TARGET_OPCODE(G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) |
447 | |
448 | /// Generic extension allowing rubbish in high bits. |
449 | HANDLE_TARGET_OPCODE(G_ANYEXT) |
450 | |
451 | /// Generic instruction to discard the high bits of a register. This differs |
452 | /// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate |
453 | /// each element individually, G_EXTRACT will typically discard the high |
454 | /// elements of the vector. |
455 | HANDLE_TARGET_OPCODE(G_TRUNC) |
456 | |
457 | /// Generic integer constant. |
458 | HANDLE_TARGET_OPCODE(G_CONSTANT) |
459 | |
460 | /// Generic floating constant. |
461 | HANDLE_TARGET_OPCODE(G_FCONSTANT) |
462 | |
463 | /// Generic va_start instruction. Stores to its one pointer operand. |
464 | HANDLE_TARGET_OPCODE(G_VASTART) |
465 | |
466 | /// Generic va_arg instruction. Stores to its one pointer operand. |
467 | HANDLE_TARGET_OPCODE(G_VAARG) |
468 | |
469 | // Generic sign extend |
470 | HANDLE_TARGET_OPCODE(G_SEXT) |
471 | HANDLE_TARGET_OPCODE(G_SEXT_INREG) |
472 | |
473 | // Generic zero extend |
474 | HANDLE_TARGET_OPCODE(G_ZEXT) |
475 | |
476 | // Generic left-shift |
477 | HANDLE_TARGET_OPCODE(G_SHL) |
478 | |
479 | // Generic logical right-shift |
480 | HANDLE_TARGET_OPCODE(G_LSHR) |
481 | |
482 | // Generic arithmetic right-shift |
483 | HANDLE_TARGET_OPCODE(G_ASHR) |
484 | |
485 | // Generic funnel left shift |
486 | HANDLE_TARGET_OPCODE(G_FSHL) |
487 | |
488 | // Generic funnel right shift |
489 | HANDLE_TARGET_OPCODE(G_FSHR) |
490 | |
491 | // Generic right rotate |
492 | HANDLE_TARGET_OPCODE(G_ROTR) |
493 | |
494 | // Generic left rotate |
495 | HANDLE_TARGET_OPCODE(G_ROTL) |
496 | |
497 | /// Generic integer-base comparison, also applicable to vectors of integers. |
498 | HANDLE_TARGET_OPCODE(G_ICMP) |
499 | |
500 | /// Generic floating-point comparison, also applicable to vectors. |
501 | HANDLE_TARGET_OPCODE(G_FCMP) |
502 | |
503 | /// Generic select. |
504 | HANDLE_TARGET_OPCODE(G_SELECT) |
505 | |
506 | /// Generic unsigned add instruction, consuming the normal operands and |
507 | /// producing the result and a carry flag. |
508 | HANDLE_TARGET_OPCODE(G_UADDO) |
509 | |
510 | /// Generic unsigned add instruction, consuming the normal operands plus a carry |
511 | /// flag, and similarly producing the result and a carry flag. |
512 | HANDLE_TARGET_OPCODE(G_UADDE) |
513 | |
514 | /// Generic unsigned sub instruction, consuming the normal operands and |
515 | /// producing the result and a carry flag. |
516 | HANDLE_TARGET_OPCODE(G_USUBO) |
517 | |
518 | /// Generic unsigned subtract instruction, consuming the normal operands plus a |
519 | /// carry flag, and similarly producing the result and a carry flag. |
520 | HANDLE_TARGET_OPCODE(G_USUBE) |
521 | |
522 | /// Generic signed add instruction, producing the result and a signed overflow |
523 | /// flag. |
524 | HANDLE_TARGET_OPCODE(G_SADDO) |
525 | |
526 | /// Generic signed add instruction, consuming the normal operands plus a carry |
527 | /// flag, and similarly producing the result and a carry flag. |
528 | HANDLE_TARGET_OPCODE(G_SADDE) |
529 | |
530 | /// Generic signed subtract instruction, producing the result and a signed |
531 | /// overflow flag. |
532 | HANDLE_TARGET_OPCODE(G_SSUBO) |
533 | |
534 | /// Generic signed sub instruction, consuming the normal operands plus a carry |
535 | /// flag, and similarly producing the result and a carry flag. |
536 | HANDLE_TARGET_OPCODE(G_SSUBE) |
537 | |
538 | /// Generic unsigned multiply instruction, producing the result and a signed |
539 | /// overflow flag. |
540 | HANDLE_TARGET_OPCODE(G_UMULO) |
541 | |
542 | /// Generic signed multiply instruction, producing the result and a signed |
543 | /// overflow flag. |
544 | HANDLE_TARGET_OPCODE(G_SMULO) |
545 | |
546 | // Multiply two numbers at twice the incoming bit width (unsigned) and return |
547 | // the high half of the result. |
548 | HANDLE_TARGET_OPCODE(G_UMULH) |
549 | |
550 | // Multiply two numbers at twice the incoming bit width (signed) and return |
551 | // the high half of the result. |
552 | HANDLE_TARGET_OPCODE(G_SMULH) |
553 | |
554 | /// Generic saturating unsigned addition. |
555 | HANDLE_TARGET_OPCODE(G_UADDSAT) |
556 | |
557 | /// Generic saturating signed addition. |
558 | HANDLE_TARGET_OPCODE(G_SADDSAT) |
559 | |
560 | /// Generic saturating unsigned subtraction. |
561 | HANDLE_TARGET_OPCODE(G_USUBSAT) |
562 | |
563 | /// Generic saturating signed subtraction. |
564 | HANDLE_TARGET_OPCODE(G_SSUBSAT) |
565 | |
566 | /// Generic saturating unsigned left shift. |
567 | HANDLE_TARGET_OPCODE(G_USHLSAT) |
568 | |
569 | /// Generic saturating signed left shift. |
570 | HANDLE_TARGET_OPCODE(G_SSHLSAT) |
571 | |
572 | // Perform signed fixed point multiplication |
573 | HANDLE_TARGET_OPCODE(G_SMULFIX) |
574 | |
575 | // Perform unsigned fixed point multiplication |
576 | HANDLE_TARGET_OPCODE(G_UMULFIX) |
577 | |
578 | // Perform signed, saturating fixed point multiplication |
579 | HANDLE_TARGET_OPCODE(G_SMULFIXSAT) |
580 | |
581 | // Perform unsigned, saturating fixed point multiplication |
582 | HANDLE_TARGET_OPCODE(G_UMULFIXSAT) |
583 | |
584 | // Perform signed fixed point division |
585 | HANDLE_TARGET_OPCODE(G_SDIVFIX) |
586 | |
587 | // Perform unsigned fixed point division |
588 | HANDLE_TARGET_OPCODE(G_UDIVFIX) |
589 | |
590 | // Perform signed, saturating fixed point division |
591 | HANDLE_TARGET_OPCODE(G_SDIVFIXSAT) |
592 | |
593 | // Perform unsigned, saturating fixed point division |
594 | HANDLE_TARGET_OPCODE(G_UDIVFIXSAT) |
595 | |
596 | /// Generic FP addition. |
597 | HANDLE_TARGET_OPCODE(G_FADD) |
598 | |
599 | /// Generic FP subtraction. |
600 | HANDLE_TARGET_OPCODE(G_FSUB) |
601 | |
602 | /// Generic FP multiplication. |
603 | HANDLE_TARGET_OPCODE(G_FMUL) |
604 | |
605 | /// Generic FMA multiplication. Behaves like llvm fma intrinsic |
606 | HANDLE_TARGET_OPCODE(G_FMA) |
607 | |
608 | /// Generic FP multiply and add. Behaves as separate fmul and fadd. |
609 | HANDLE_TARGET_OPCODE(G_FMAD) |
610 | |
611 | /// Generic FP division. |
612 | HANDLE_TARGET_OPCODE(G_FDIV) |
613 | |
614 | /// Generic FP remainder. |
615 | HANDLE_TARGET_OPCODE(G_FREM) |
616 | |
617 | /// Generic FP exponentiation. |
618 | HANDLE_TARGET_OPCODE(G_FPOW) |
619 | |
620 | /// Generic FP exponentiation, with an integer exponent. |
621 | HANDLE_TARGET_OPCODE(G_FPOWI) |
622 | |
623 | /// Generic base-e exponential of a value. |
624 | HANDLE_TARGET_OPCODE(G_FEXP) |
625 | |
626 | /// Generic base-2 exponential of a value. |
627 | HANDLE_TARGET_OPCODE(G_FEXP2) |
628 | |
629 | /// Generic base-10 exponential of a value. |
630 | HANDLE_TARGET_OPCODE(G_FEXP10) |
631 | |
632 | /// Floating point base-e logarithm of a value. |
633 | HANDLE_TARGET_OPCODE(G_FLOG) |
634 | |
635 | /// Floating point base-2 logarithm of a value. |
636 | HANDLE_TARGET_OPCODE(G_FLOG2) |
637 | |
638 | /// Floating point base-10 logarithm of a value. |
639 | HANDLE_TARGET_OPCODE(G_FLOG10) |
640 | |
641 | /// Floating point x * 2^n |
642 | HANDLE_TARGET_OPCODE(G_FLDEXP) |
643 | |
644 | /// Floating point extract fraction and exponent. |
645 | HANDLE_TARGET_OPCODE(G_FFREXP) |
646 | |
647 | /// Generic FP negation. |
648 | HANDLE_TARGET_OPCODE(G_FNEG) |
649 | |
650 | /// Generic FP extension. |
651 | HANDLE_TARGET_OPCODE(G_FPEXT) |
652 | |
653 | /// Generic float to signed-int conversion |
654 | HANDLE_TARGET_OPCODE(G_FPTRUNC) |
655 | |
656 | /// Generic float to signed-int conversion |
657 | HANDLE_TARGET_OPCODE(G_FPTOSI) |
658 | |
659 | /// Generic float to unsigned-int conversion |
660 | HANDLE_TARGET_OPCODE(G_FPTOUI) |
661 | |
662 | /// Generic signed-int to float conversion |
663 | HANDLE_TARGET_OPCODE(G_SITOFP) |
664 | |
665 | /// Generic unsigned-int to float conversion |
666 | HANDLE_TARGET_OPCODE(G_UITOFP) |
667 | |
668 | /// Generic FP absolute value. |
669 | HANDLE_TARGET_OPCODE(G_FABS) |
670 | |
671 | /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does |
672 | /// not require that X and Y have the same type, just that they are both |
673 | /// floating point. X and the result must have the same type. FCOPYSIGN(f32, |
674 | /// f64) is allowed. |
675 | HANDLE_TARGET_OPCODE(G_FCOPYSIGN) |
676 | |
677 | /// Generic test for floating-point class. |
678 | HANDLE_TARGET_OPCODE(G_IS_FPCLASS) |
679 | |
680 | /// Generic FP canonicalize value. |
681 | HANDLE_TARGET_OPCODE(G_FCANONICALIZE) |
682 | |
683 | /// FP min/max matching libm's fmin/fmax |
684 | HANDLE_TARGET_OPCODE(G_FMINNUM) |
685 | HANDLE_TARGET_OPCODE(G_FMAXNUM) |
686 | |
687 | /// FP min/max matching IEEE-754 2008's minnum/maxnum semantics. |
688 | HANDLE_TARGET_OPCODE(G_FMINNUM_IEEE) |
689 | HANDLE_TARGET_OPCODE(G_FMAXNUM_IEEE) |
690 | |
691 | /// FP min/max matching IEEE-754 2018 draft semantics. |
692 | HANDLE_TARGET_OPCODE(G_FMINIMUM) |
693 | HANDLE_TARGET_OPCODE(G_FMAXIMUM) |
694 | |
695 | /// Access to FP environment. |
696 | HANDLE_TARGET_OPCODE(G_GET_FPENV) |
697 | HANDLE_TARGET_OPCODE(G_SET_FPENV) |
698 | HANDLE_TARGET_OPCODE(G_RESET_FPENV) |
699 | HANDLE_TARGET_OPCODE(G_GET_FPMODE) |
700 | HANDLE_TARGET_OPCODE(G_SET_FPMODE) |
701 | HANDLE_TARGET_OPCODE(G_RESET_FPMODE) |
702 | |
703 | /// Generic pointer offset |
704 | HANDLE_TARGET_OPCODE(G_PTR_ADD) |
705 | |
706 | /// Clear the specified bits in a pointer. |
707 | HANDLE_TARGET_OPCODE(G_PTRMASK) |
708 | |
709 | /// Generic signed integer minimum. |
710 | HANDLE_TARGET_OPCODE(G_SMIN) |
711 | |
712 | /// Generic signed integer maximum. |
713 | HANDLE_TARGET_OPCODE(G_SMAX) |
714 | |
715 | /// Generic unsigned integer maximum. |
716 | HANDLE_TARGET_OPCODE(G_UMIN) |
717 | |
718 | /// Generic unsigned integer maximum. |
719 | HANDLE_TARGET_OPCODE(G_UMAX) |
720 | |
721 | /// Generic integer absolute value. |
722 | HANDLE_TARGET_OPCODE(G_ABS) |
723 | |
724 | HANDLE_TARGET_OPCODE(G_LROUND) |
725 | HANDLE_TARGET_OPCODE(G_LLROUND) |
726 | |
727 | /// Generic BRANCH instruction. This is an unconditional branch. |
728 | HANDLE_TARGET_OPCODE(G_BR) |
729 | |
730 | /// Generic branch to jump table entry. |
731 | HANDLE_TARGET_OPCODE(G_BRJT) |
732 | |
733 | /// Generic vscale. |
734 | HANDLE_TARGET_OPCODE(G_VSCALE) |
735 | |
736 | /// Generic insert subvector. |
737 | HANDLE_TARGET_OPCODE(G_INSERT_SUBVECTOR) |
738 | |
739 | /// Generic extract subvector. |
740 | HANDLE_TARGET_OPCODE() |
741 | |
742 | /// Generic insertelement. |
743 | HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) |
744 | |
745 | /// Generic extractelement. |
746 | HANDLE_TARGET_OPCODE() |
747 | |
748 | /// Generic shufflevector. |
749 | HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) |
750 | |
751 | /// Generic splatvector. |
752 | HANDLE_TARGET_OPCODE(G_SPLAT_VECTOR) |
753 | |
754 | /// Generic count trailing zeroes. |
755 | HANDLE_TARGET_OPCODE(G_CTTZ) |
756 | |
757 | /// Same as above, undefined for zero inputs. |
758 | HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF) |
759 | |
760 | /// Generic count leading zeroes. |
761 | HANDLE_TARGET_OPCODE(G_CTLZ) |
762 | |
763 | /// Same as above, undefined for zero inputs. |
764 | HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF) |
765 | |
766 | /// Generic count bits. |
767 | HANDLE_TARGET_OPCODE(G_CTPOP) |
768 | |
769 | /// Generic byte swap. |
770 | HANDLE_TARGET_OPCODE(G_BSWAP) |
771 | |
772 | /// Generic bit reverse. |
773 | HANDLE_TARGET_OPCODE(G_BITREVERSE) |
774 | |
775 | /// Floating point ceil. |
776 | HANDLE_TARGET_OPCODE(G_FCEIL) |
777 | |
778 | /// Floating point cosine. |
779 | HANDLE_TARGET_OPCODE(G_FCOS) |
780 | |
781 | /// Floating point sine. |
782 | HANDLE_TARGET_OPCODE(G_FSIN) |
783 | |
784 | /// Floating point square root. |
785 | HANDLE_TARGET_OPCODE(G_FSQRT) |
786 | |
787 | /// Floating point floor. |
788 | HANDLE_TARGET_OPCODE(G_FFLOOR) |
789 | |
790 | /// Floating point round to next integer. |
791 | HANDLE_TARGET_OPCODE(G_FRINT) |
792 | |
793 | /// Floating point round to nearest integer. |
794 | HANDLE_TARGET_OPCODE(G_FNEARBYINT) |
795 | |
796 | /// Generic AddressSpaceCast. |
797 | HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) |
798 | |
799 | /// Generic block address |
800 | HANDLE_TARGET_OPCODE(G_BLOCK_ADDR) |
801 | |
802 | /// Generic jump table address |
803 | HANDLE_TARGET_OPCODE(G_JUMP_TABLE) |
804 | |
805 | /// Generic dynamic stack allocation. |
806 | HANDLE_TARGET_OPCODE(G_DYN_STACKALLOC) |
807 | |
808 | /// Generic stack pointer save. |
809 | HANDLE_TARGET_OPCODE(G_STACKSAVE) |
810 | |
811 | /// Generic stack pointer restore. |
812 | HANDLE_TARGET_OPCODE(G_STACKRESTORE) |
813 | |
814 | /// Strict floating point instructions. |
815 | HANDLE_TARGET_OPCODE(G_STRICT_FADD) |
816 | HANDLE_TARGET_OPCODE(G_STRICT_FSUB) |
817 | HANDLE_TARGET_OPCODE(G_STRICT_FMUL) |
818 | HANDLE_TARGET_OPCODE(G_STRICT_FDIV) |
819 | HANDLE_TARGET_OPCODE(G_STRICT_FREM) |
820 | HANDLE_TARGET_OPCODE(G_STRICT_FMA) |
821 | HANDLE_TARGET_OPCODE(G_STRICT_FSQRT) |
822 | HANDLE_TARGET_OPCODE(G_STRICT_FLDEXP) |
823 | |
824 | /// read_register intrinsic |
825 | HANDLE_TARGET_OPCODE(G_READ_REGISTER) |
826 | |
827 | /// write_register intrinsic |
828 | HANDLE_TARGET_OPCODE(G_WRITE_REGISTER) |
829 | |
830 | /// llvm.memcpy intrinsic |
831 | HANDLE_TARGET_OPCODE(G_MEMCPY) |
832 | |
833 | /// llvm.memcpy.inline intrinsic |
834 | HANDLE_TARGET_OPCODE(G_MEMCPY_INLINE) |
835 | |
836 | /// llvm.memmove intrinsic |
837 | HANDLE_TARGET_OPCODE(G_MEMMOVE) |
838 | |
839 | /// llvm.memset intrinsic |
840 | HANDLE_TARGET_OPCODE(G_MEMSET) |
841 | HANDLE_TARGET_OPCODE(G_BZERO) |
842 | |
843 | /// llvm.trap, llvm.debugtrap and llvm.ubsantrap intrinsics |
844 | HANDLE_TARGET_OPCODE(G_TRAP) |
845 | HANDLE_TARGET_OPCODE(G_DEBUGTRAP) |
846 | HANDLE_TARGET_OPCODE(G_UBSANTRAP) |
847 | |
848 | /// Vector reductions |
849 | HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FADD) |
850 | HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FMUL) |
851 | HANDLE_TARGET_OPCODE(G_VECREDUCE_FADD) |
852 | HANDLE_TARGET_OPCODE(G_VECREDUCE_FMUL) |
853 | HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAX) |
854 | HANDLE_TARGET_OPCODE(G_VECREDUCE_FMIN) |
855 | HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAXIMUM) |
856 | HANDLE_TARGET_OPCODE(G_VECREDUCE_FMINIMUM) |
857 | HANDLE_TARGET_OPCODE(G_VECREDUCE_ADD) |
858 | HANDLE_TARGET_OPCODE(G_VECREDUCE_MUL) |
859 | HANDLE_TARGET_OPCODE(G_VECREDUCE_AND) |
860 | HANDLE_TARGET_OPCODE(G_VECREDUCE_OR) |
861 | HANDLE_TARGET_OPCODE(G_VECREDUCE_XOR) |
862 | HANDLE_TARGET_OPCODE(G_VECREDUCE_SMAX) |
863 | HANDLE_TARGET_OPCODE(G_VECREDUCE_SMIN) |
864 | HANDLE_TARGET_OPCODE(G_VECREDUCE_UMAX) |
865 | HANDLE_TARGET_OPCODE(G_VECREDUCE_UMIN) |
866 | |
867 | HANDLE_TARGET_OPCODE(G_SBFX) |
868 | HANDLE_TARGET_OPCODE(G_UBFX) |
869 | |
870 | /// Marker for the end of the generic opcode. |
871 | /// This is used to check if an opcode is in the range of the |
872 | /// generic opcodes. |
873 | HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_UBFX) |
874 | |
875 | /// BUILTIN_OP_END - This must be the last enum value in this list. |
876 | /// The target-specific post-isel opcode values start here. |
877 | HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) |
878 | |