1//===- CodeGen/MachineInstrBuilder.h - Simplify creation of MIs --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file exposes a function named BuildMI, which is useful for dramatically
10// simplifying how MachineInstr's are created. It allows use of code like this:
11//
12// MIMetadata MIMD(MI); // Propagates DebugLoc and other metadata
13// M = BuildMI(MBB, MI, MIMD, TII.get(X86::ADD8rr), Dst)
14// .addReg(argVal1)
15// .addReg(argVal2);
16//
17//===----------------------------------------------------------------------===//
18
19#ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
20#define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
21
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/CodeGen/GlobalISel/Utils.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineInstrBundle.h"
28#include "llvm/CodeGen/MachineOperand.h"
29#include "llvm/CodeGen/TargetRegisterInfo.h"
30#include "llvm/IR/InstrTypes.h"
31#include "llvm/IR/Intrinsics.h"
32#include "llvm/Support/Compiler.h"
33#include "llvm/Support/ErrorHandling.h"
34#include <cassert>
35#include <cstdint>
36
37namespace llvm {
38
39class MCInstrDesc;
40class MDNode;
41
42namespace RegState {
43
44// Keep this in sync with the table in MIRLangRef.rst.
45enum {
46 /// Register definition.
47 Define = 0x2,
48 /// Not emitted register (e.g. carry, or temporary result).
49 Implicit = 0x4,
50 /// The last use of a register.
51 Kill = 0x8,
52 /// Unused definition.
53 Dead = 0x10,
54 /// Value of the register doesn't matter.
55 Undef = 0x20,
56 /// Register definition happens before uses.
57 EarlyClobber = 0x40,
58 /// Register 'use' is for debugging purpose.
59 Debug = 0x80,
60 /// Register reads a value that is defined inside the same instruction or
61 /// bundle.
62 InternalRead = 0x100,
63 /// Register that may be renamed.
64 Renamable = 0x200,
65 DefineNoRead = Define | Undef,
66 ImplicitDefine = Implicit | Define,
67 ImplicitKill = Implicit | Kill
68};
69
70} // end namespace RegState
71
72class MachineInstrBuilder {
73 MachineFunction *MF = nullptr;
74 MachineInstr *MI = nullptr;
75
76public:
77 MachineInstrBuilder() = default;
78
79 /// Create a MachineInstrBuilder for manipulating an existing instruction.
80 /// F must be the machine function that was used to allocate I.
81 MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {}
82 MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I)
83 : MF(&F), MI(&*I) {}
84
85 /// Allow automatic conversion to the machine instruction we are working on.
86 operator MachineInstr*() const { return MI; }
87 MachineInstr *operator->() const { return MI; }
88 operator MachineBasicBlock::iterator() const { return MI; }
89
90 /// If conversion operators fail, use this method to get the MachineInstr
91 /// explicitly.
92 MachineInstr *getInstr() const { return MI; }
93
94 /// Get the register for the operand index.
95 /// The operand at the index should be a register (asserted by
96 /// MachineOperand).
97 Register getReg(unsigned Idx) const { return MI->getOperand(i: Idx).getReg(); }
98
99 /// Add a new virtual register operand.
100 const MachineInstrBuilder &addReg(Register RegNo, unsigned flags = 0,
101 unsigned SubReg = 0) const {
102 assert((flags & 0x1) == 0 &&
103 "Passing in 'true' to addReg is forbidden! Use enums instead.");
104 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateReg(Reg: RegNo,
105 isDef: flags & RegState::Define,
106 isImp: flags & RegState::Implicit,
107 isKill: flags & RegState::Kill,
108 isDead: flags & RegState::Dead,
109 isUndef: flags & RegState::Undef,
110 isEarlyClobber: flags & RegState::EarlyClobber,
111 SubReg,
112 isDebug: flags & RegState::Debug,
113 isInternalRead: flags & RegState::InternalRead,
114 isRenamable: flags & RegState::Renamable));
115 return *this;
116 }
117
118 /// Add a virtual register definition operand.
119 const MachineInstrBuilder &addDef(Register RegNo, unsigned Flags = 0,
120 unsigned SubReg = 0) const {
121 return addReg(RegNo, flags: Flags | RegState::Define, SubReg);
122 }
123
124 /// Add a virtual register use operand. It is an error for Flags to contain
125 /// `RegState::Define` when calling this function.
126 const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0,
127 unsigned SubReg = 0) const {
128 assert(!(Flags & RegState::Define) &&
129 "Misleading addUse defines register, use addReg instead.");
130 return addReg(RegNo, flags: Flags, SubReg);
131 }
132
133 /// Add a new immediate operand.
134 const MachineInstrBuilder &addImm(int64_t Val) const {
135 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateImm(Val));
136 return *this;
137 }
138
139 const MachineInstrBuilder &addCImm(const ConstantInt *Val) const {
140 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateCImm(CI: Val));
141 return *this;
142 }
143
144 const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
145 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateFPImm(CFP: Val));
146 return *this;
147 }
148
149 const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB,
150 unsigned TargetFlags = 0) const {
151 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateMBB(MBB, TargetFlags));
152 return *this;
153 }
154
155 const MachineInstrBuilder &addFrameIndex(int Idx) const {
156 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateFI(Idx));
157 return *this;
158 }
159
160 const MachineInstrBuilder &
161 addConstantPoolIndex(unsigned Idx, int Offset = 0,
162 unsigned TargetFlags = 0) const {
163 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
164 return *this;
165 }
166
167 const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0,
168 unsigned TargetFlags = 0) const {
169 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateTargetIndex(Idx, Offset,
170 TargetFlags));
171 return *this;
172 }
173
174 const MachineInstrBuilder &addJumpTableIndex(unsigned Idx,
175 unsigned TargetFlags = 0) const {
176 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateJTI(Idx, TargetFlags));
177 return *this;
178 }
179
180 const MachineInstrBuilder &addGlobalAddress(const GlobalValue *GV,
181 int64_t Offset = 0,
182 unsigned TargetFlags = 0) const {
183 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateGA(GV, Offset, TargetFlags));
184 return *this;
185 }
186
187 const MachineInstrBuilder &addExternalSymbol(const char *FnName,
188 unsigned TargetFlags = 0) const {
189 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateES(SymName: FnName, TargetFlags));
190 return *this;
191 }
192
193 const MachineInstrBuilder &addBlockAddress(const BlockAddress *BA,
194 int64_t Offset = 0,
195 unsigned TargetFlags = 0) const {
196 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateBA(BA, Offset, TargetFlags));
197 return *this;
198 }
199
200 const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const {
201 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateRegMask(Mask));
202 return *this;
203 }
204
205 const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const {
206 MI->addMemOperand(MF&: *MF, MO: MMO);
207 return *this;
208 }
209
210 const MachineInstrBuilder &
211 setMemRefs(ArrayRef<MachineMemOperand *> MMOs) const {
212 MI->setMemRefs(MF&: *MF, MemRefs: MMOs);
213 return *this;
214 }
215
216 const MachineInstrBuilder &cloneMemRefs(const MachineInstr &OtherMI) const {
217 MI->cloneMemRefs(MF&: *MF, MI: OtherMI);
218 return *this;
219 }
220
221 const MachineInstrBuilder &
222 cloneMergedMemRefs(ArrayRef<const MachineInstr *> OtherMIs) const {
223 MI->cloneMergedMemRefs(MF&: *MF, MIs: OtherMIs);
224 return *this;
225 }
226
227 const MachineInstrBuilder &add(const MachineOperand &MO) const {
228 MI->addOperand(MF&: *MF, Op: MO);
229 return *this;
230 }
231
232 const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const {
233 for (const MachineOperand &MO : MOs)
234 MI->addOperand(MF&: *MF, Op: MO);
235 return *this;
236 }
237
238 const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
239 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateMetadata(Meta: MD));
240 assert((MI->isDebugValueLike() ? static_cast<bool>(MI->getDebugVariable())
241 : true) &&
242 "first MDNode argument of a DBG_VALUE not a variable");
243 assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel())
244 : true) &&
245 "first MDNode argument of a DBG_LABEL not a label");
246 return *this;
247 }
248
249 const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {
250 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateCFIIndex(CFIIndex));
251 return *this;
252 }
253
254 const MachineInstrBuilder &addIntrinsicID(Intrinsic::ID ID) const {
255 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateIntrinsicID(ID));
256 return *this;
257 }
258
259 const MachineInstrBuilder &addPredicate(CmpInst::Predicate Pred) const {
260 MI->addOperand(MF&: *MF, Op: MachineOperand::CreatePredicate(Pred));
261 return *this;
262 }
263
264 const MachineInstrBuilder &addShuffleMask(ArrayRef<int> Val) const {
265 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateShuffleMask(Mask: Val));
266 return *this;
267 }
268
269 const MachineInstrBuilder &addSym(MCSymbol *Sym,
270 unsigned char TargetFlags = 0) const {
271 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateMCSymbol(Sym, TargetFlags));
272 return *this;
273 }
274
275 const MachineInstrBuilder &setMIFlags(unsigned Flags) const {
276 MI->setFlags(Flags);
277 return *this;
278 }
279
280 const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const {
281 MI->setFlag(Flag);
282 return *this;
283 }
284
285 const MachineInstrBuilder &setOperandDead(unsigned OpIdx) const {
286 MI->getOperand(i: OpIdx).setIsDead();
287 return *this;
288 }
289
290 // Add a displacement from an existing MachineOperand with an added offset.
291 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
292 unsigned char TargetFlags = 0) const {
293 // If caller specifies new TargetFlags then use it, otherwise the
294 // default behavior is to copy the target flags from the existing
295 // MachineOperand. This means if the caller wants to clear the
296 // target flags it needs to do so explicitly.
297 if (0 == TargetFlags)
298 TargetFlags = Disp.getTargetFlags();
299
300 switch (Disp.getType()) {
301 default:
302 llvm_unreachable("Unhandled operand type in addDisp()");
303 case MachineOperand::MO_Immediate:
304 return addImm(Val: Disp.getImm() + off);
305 case MachineOperand::MO_ConstantPoolIndex:
306 return addConstantPoolIndex(Idx: Disp.getIndex(), Offset: Disp.getOffset() + off,
307 TargetFlags);
308 case MachineOperand::MO_GlobalAddress:
309 return addGlobalAddress(GV: Disp.getGlobal(), Offset: Disp.getOffset() + off,
310 TargetFlags);
311 case MachineOperand::MO_BlockAddress:
312 return addBlockAddress(BA: Disp.getBlockAddress(), Offset: Disp.getOffset() + off,
313 TargetFlags);
314 case MachineOperand::MO_JumpTableIndex:
315 assert(off == 0 && "cannot create offset into jump tables");
316 return addJumpTableIndex(Idx: Disp.getIndex(), TargetFlags);
317 }
318 }
319
320 const MachineInstrBuilder &setPCSections(MDNode *MD) const {
321 if (MD)
322 MI->setPCSections(MF&: *MF, MD);
323 return *this;
324 }
325
326 const MachineInstrBuilder &setMMRAMetadata(MDNode *MMRA) const {
327 if (MMRA)
328 MI->setMMRAMetadata(MF&: *MF, MMRAs: MMRA);
329 return *this;
330 }
331
332 /// Copy all the implicit operands from OtherMI onto this one.
333 const MachineInstrBuilder &
334 copyImplicitOps(const MachineInstr &OtherMI) const {
335 MI->copyImplicitOps(MF&: *MF, MI: OtherMI);
336 return *this;
337 }
338
339 bool constrainAllUses(const TargetInstrInfo &TII,
340 const TargetRegisterInfo &TRI,
341 const RegisterBankInfo &RBI) const {
342 return constrainSelectedInstRegOperands(I&: *MI, TII, TRI, RBI);
343 }
344};
345
346/// Set of metadata that should be preserved when using BuildMI(). This provides
347/// a more convenient way of preserving DebugLoc, PCSections and MMRA.
348class MIMetadata {
349public:
350 MIMetadata() = default;
351 MIMetadata(DebugLoc DL, MDNode *PCSections = nullptr, MDNode *MMRA = nullptr)
352 : DL(std::move(DL)), PCSections(PCSections), MMRA(MMRA) {}
353 MIMetadata(const DILocation *DI, MDNode *PCSections = nullptr,
354 MDNode *MMRA = nullptr)
355 : DL(DI), PCSections(PCSections), MMRA(MMRA) {}
356 explicit MIMetadata(const Instruction &From)
357 : DL(From.getDebugLoc()),
358 PCSections(From.getMetadata(KindID: LLVMContext::MD_pcsections)) {}
359 explicit MIMetadata(const MachineInstr &From)
360 : DL(From.getDebugLoc()), PCSections(From.getPCSections()) {}
361
362 const DebugLoc &getDL() const { return DL; }
363 MDNode *getPCSections() const { return PCSections; }
364 MDNode *getMMRAMetadata() const { return MMRA; }
365
366private:
367 DebugLoc DL;
368 MDNode *PCSections = nullptr;
369 MDNode *MMRA = nullptr;
370};
371
372/// Builder interface. Specify how to create the initial instruction itself.
373inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD,
374 const MCInstrDesc &MCID) {
375 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL: MIMD.getDL()))
376 .setPCSections(MIMD.getPCSections())
377 .setMMRAMetadata(MIMD.getMMRAMetadata());
378}
379
380/// This version of the builder sets up the first operand as a
381/// destination virtual register.
382inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD,
383 const MCInstrDesc &MCID, Register DestReg) {
384 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL: MIMD.getDL()))
385 .setPCSections(MIMD.getPCSections())
386 .setMMRAMetadata(MIMD.getMMRAMetadata())
387 .addReg(RegNo: DestReg, flags: RegState::Define);
388}
389
390/// This version of the builder inserts the newly-built instruction before
391/// the given position in the given MachineBasicBlock, and sets up the first
392/// operand as a destination virtual register.
393inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
394 MachineBasicBlock::iterator I,
395 const MIMetadata &MIMD,
396 const MCInstrDesc &MCID, Register DestReg) {
397 MachineFunction &MF = *BB.getParent();
398 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL: MIMD.getDL());
399 BB.insert(I, MI);
400 return MachineInstrBuilder(MF, MI)
401 .setPCSections(MIMD.getPCSections())
402 .setMMRAMetadata(MIMD.getMMRAMetadata())
403 .addReg(RegNo: DestReg, flags: RegState::Define);
404}
405
406/// This version of the builder inserts the newly-built instruction before
407/// the given position in the given MachineBasicBlock, and sets up the first
408/// operand as a destination virtual register.
409///
410/// If \c I is inside a bundle, then the newly inserted \a MachineInstr is
411/// added to the same bundle.
412inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
413 MachineBasicBlock::instr_iterator I,
414 const MIMetadata &MIMD,
415 const MCInstrDesc &MCID, Register DestReg) {
416 MachineFunction &MF = *BB.getParent();
417 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL: MIMD.getDL());
418 BB.insert(I, M: MI);
419 return MachineInstrBuilder(MF, MI)
420 .setPCSections(MIMD.getPCSections())
421 .setMMRAMetadata(MIMD.getMMRAMetadata())
422 .addReg(RegNo: DestReg, flags: RegState::Define);
423}
424
425inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
426 const MIMetadata &MIMD,
427 const MCInstrDesc &MCID, Register DestReg) {
428 // Calling the overload for instr_iterator is always correct. However, the
429 // definition is not available in headers, so inline the check.
430 if (I.isInsideBundle())
431 return BuildMI(BB, I: MachineBasicBlock::instr_iterator(I), MIMD, MCID,
432 DestReg);
433 return BuildMI(BB, I: MachineBasicBlock::iterator(I), MIMD, MCID, DestReg);
434}
435
436inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
437 const MIMetadata &MIMD,
438 const MCInstrDesc &MCID, Register DestReg) {
439 return BuildMI(BB, I&: *I, MIMD, MCID, DestReg);
440}
441
442/// This version of the builder inserts the newly-built instruction before the
443/// given position in the given MachineBasicBlock, and does NOT take a
444/// destination register.
445inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
446 MachineBasicBlock::iterator I,
447 const MIMetadata &MIMD,
448 const MCInstrDesc &MCID) {
449 MachineFunction &MF = *BB.getParent();
450 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL: MIMD.getDL());
451 BB.insert(I, MI);
452 return MachineInstrBuilder(MF, MI)
453 .setPCSections(MIMD.getPCSections())
454 .setMMRAMetadata(MIMD.getMMRAMetadata());
455}
456
457inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
458 MachineBasicBlock::instr_iterator I,
459 const MIMetadata &MIMD,
460 const MCInstrDesc &MCID) {
461 MachineFunction &MF = *BB.getParent();
462 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL: MIMD.getDL());
463 BB.insert(I, M: MI);
464 return MachineInstrBuilder(MF, MI)
465 .setPCSections(MIMD.getPCSections())
466 .setMMRAMetadata(MIMD.getMMRAMetadata());
467}
468
469inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
470 const MIMetadata &MIMD,
471 const MCInstrDesc &MCID) {
472 // Calling the overload for instr_iterator is always correct. However, the
473 // definition is not available in headers, so inline the check.
474 if (I.isInsideBundle())
475 return BuildMI(BB, I: MachineBasicBlock::instr_iterator(I), MIMD, MCID);
476 return BuildMI(BB, I: MachineBasicBlock::iterator(I), MIMD, MCID);
477}
478
479inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
480 const MIMetadata &MIMD,
481 const MCInstrDesc &MCID) {
482 return BuildMI(BB, I&: *I, MIMD, MCID);
483}
484
485/// This version of the builder inserts the newly-built instruction at the end
486/// of the given MachineBasicBlock, and does NOT take a destination register.
487inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
488 const MIMetadata &MIMD,
489 const MCInstrDesc &MCID) {
490 return BuildMI(BB&: *BB, I: BB->end(), MIMD, MCID);
491}
492
493/// This version of the builder inserts the newly-built instruction at the
494/// end of the given MachineBasicBlock, and sets up the first operand as a
495/// destination virtual register.
496inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
497 const MIMetadata &MIMD,
498 const MCInstrDesc &MCID, Register DestReg) {
499 return BuildMI(BB&: *BB, I: BB->end(), MIMD, MCID, DestReg);
500}
501
502/// This version of the builder builds a DBG_VALUE intrinsic
503/// for either a value in a register or a register-indirect
504/// address. The convention is that a DBG_VALUE is indirect iff the
505/// second operand is an immediate.
506LLVM_ABI MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
507 const MCInstrDesc &MCID, bool IsIndirect,
508 Register Reg, const MDNode *Variable,
509 const MDNode *Expr);
510
511/// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
512/// for a MachineOperand.
513LLVM_ABI MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
514 const MCInstrDesc &MCID, bool IsIndirect,
515 ArrayRef<MachineOperand> MOs,
516 const MDNode *Variable,
517 const MDNode *Expr);
518
519/// This version of the builder builds a DBG_VALUE intrinsic
520/// for either a value in a register or a register-indirect
521/// address and inserts it at position I.
522LLVM_ABI MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
523 MachineBasicBlock::iterator I,
524 const DebugLoc &DL,
525 const MCInstrDesc &MCID, bool IsIndirect,
526 Register Reg, const MDNode *Variable,
527 const MDNode *Expr);
528
529/// This version of the builder builds a DBG_VALUE, DBG_INSTR_REF, or
530/// DBG_VALUE_LIST intrinsic for a machine operand and inserts it at position I.
531LLVM_ABI MachineInstrBuilder BuildMI(
532 MachineBasicBlock &BB, MachineBasicBlock::iterator I, const DebugLoc &DL,
533 const MCInstrDesc &MCID, bool IsIndirect, ArrayRef<MachineOperand> MOs,
534 const MDNode *Variable, const MDNode *Expr);
535
536/// Clone a DBG_VALUE whose value has been spilled to FrameIndex.
537LLVM_ABI MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,
538 MachineBasicBlock::iterator I,
539 const MachineInstr &Orig,
540 int FrameIndex, Register SpillReg);
541LLVM_ABI MachineInstr *buildDbgValueForSpill(
542 MachineBasicBlock &BB, MachineBasicBlock::iterator I,
543 const MachineInstr &Orig, int FrameIndex,
544 const SmallVectorImpl<const MachineOperand *> &SpilledOperands);
545
546/// Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when
547/// modifying an instruction in place while iterating over a basic block.
548LLVM_ABI void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex,
549 Register Reg);
550
551inline unsigned getDefRegState(bool B) {
552 return B ? RegState::Define : 0;
553}
554inline unsigned getImplRegState(bool B) {
555 return B ? RegState::Implicit : 0;
556}
557inline unsigned getKillRegState(bool B) {
558 return B ? RegState::Kill : 0;
559}
560inline unsigned getDeadRegState(bool B) {
561 return B ? RegState::Dead : 0;
562}
563inline unsigned getUndefRegState(bool B) {
564 return B ? RegState::Undef : 0;
565}
566inline unsigned getInternalReadRegState(bool B) {
567 return B ? RegState::InternalRead : 0;
568}
569inline unsigned getDebugRegState(bool B) {
570 return B ? RegState::Debug : 0;
571}
572inline unsigned getRenamableRegState(bool B) {
573 return B ? RegState::Renamable : 0;
574}
575
576/// Get all register state flags from machine operand \p RegOp.
577inline unsigned getRegState(const MachineOperand &RegOp) {
578 assert(RegOp.isReg() && "Not a register operand");
579 return getDefRegState(B: RegOp.isDef()) | getImplRegState(B: RegOp.isImplicit()) |
580 getKillRegState(B: RegOp.isKill()) | getDeadRegState(B: RegOp.isDead()) |
581 getUndefRegState(B: RegOp.isUndef()) |
582 getInternalReadRegState(B: RegOp.isInternalRead()) |
583 getDebugRegState(B: RegOp.isDebug()) |
584 getRenamableRegState(B: RegOp.getReg().isPhysical() &&
585 RegOp.isRenamable());
586}
587
588/// Helper class for constructing bundles of MachineInstrs.
589///
590/// MIBundleBuilder can create a bundle from scratch by inserting new
591/// MachineInstrs one at a time, or it can create a bundle from a sequence of
592/// existing MachineInstrs in a basic block.
593class MIBundleBuilder {
594 MachineBasicBlock &MBB;
595 MachineBasicBlock::instr_iterator Begin;
596 MachineBasicBlock::instr_iterator End;
597
598public:
599 /// Create an MIBundleBuilder that inserts instructions into a new bundle in
600 /// BB above the bundle or instruction at Pos.
601 MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos)
602 : MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {}
603
604 /// Create a bundle from the sequence of instructions between B and E.
605 MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B,
606 MachineBasicBlock::iterator E)
607 : MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) {
608 assert(B != E && "No instructions to bundle");
609 ++B;
610 while (B != E) {
611 MachineInstr &MI = *B;
612 ++B;
613 MI.bundleWithPred();
614 }
615 }
616
617 /// Create an MIBundleBuilder representing an existing instruction or bundle
618 /// that has MI as its head.
619 explicit MIBundleBuilder(MachineInstr *MI)
620 : MBB(*MI->getParent()), Begin(MI),
621 End(getBundleEnd(I: MI->getIterator())) {}
622
623 /// Return a reference to the basic block containing this bundle.
624 MachineBasicBlock &getMBB() const { return MBB; }
625
626 /// Return true if no instructions have been inserted in this bundle yet.
627 /// Empty bundles aren't representable in a MachineBasicBlock.
628 bool empty() const { return Begin == End; }
629
630 /// Return an iterator to the first bundled instruction.
631 MachineBasicBlock::instr_iterator begin() const { return Begin; }
632
633 /// Return an iterator beyond the last bundled instruction.
634 MachineBasicBlock::instr_iterator end() const { return End; }
635
636 /// Insert MI into this bundle before I which must point to an instruction in
637 /// the bundle, or end().
638 MIBundleBuilder &insert(MachineBasicBlock::instr_iterator I,
639 MachineInstr *MI) {
640 MBB.insert(I, M: MI);
641 if (I == Begin) {
642 if (!empty())
643 MI->bundleWithSucc();
644 Begin = MI->getIterator();
645 return *this;
646 }
647 if (I == End) {
648 MI->bundleWithPred();
649 return *this;
650 }
651 // MI was inserted in the middle of the bundle, so its neighbors' flags are
652 // already fine. Update MI's bundle flags manually.
653 MI->setFlag(MachineInstr::BundledPred);
654 MI->setFlag(MachineInstr::BundledSucc);
655 return *this;
656 }
657
658 /// Insert MI into MBB by prepending it to the instructions in the bundle.
659 /// MI will become the first instruction in the bundle.
660 MIBundleBuilder &prepend(MachineInstr *MI) {
661 return insert(I: begin(), MI);
662 }
663
664 /// Insert MI into MBB by appending it to the instructions in the bundle.
665 /// MI will become the last instruction in the bundle.
666 MIBundleBuilder &append(MachineInstr *MI) {
667 return insert(I: end(), MI);
668 }
669};
670
671} // end namespace llvm
672
673#endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H
674

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source code of llvm/include/llvm/CodeGen/MachineInstrBuilder.h