1 | //===- llvm/CodeGen/TargetSubtargetInfo.h - Target Information --*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file describes the subtarget options of a Target machine. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #ifndef LLVM_CODEGEN_TARGETSUBTARGETINFO_H |
14 | #define LLVM_CODEGEN_TARGETSUBTARGETINFO_H |
15 | |
16 | #include "llvm/ADT/ArrayRef.h" |
17 | #include "llvm/ADT/SmallVector.h" |
18 | #include "llvm/ADT/StringRef.h" |
19 | #include "llvm/CodeGen/MacroFusion.h" |
20 | #include "llvm/CodeGen/PBQPRAConstraint.h" |
21 | #include "llvm/CodeGen/SchedulerRegistry.h" |
22 | #include "llvm/IR/GlobalValue.h" |
23 | #include "llvm/MC/MCSubtargetInfo.h" |
24 | #include "llvm/Support/CodeGen.h" |
25 | #include <memory> |
26 | #include <vector> |
27 | |
28 | namespace llvm { |
29 | |
30 | class APInt; |
31 | class MachineFunction; |
32 | class ScheduleDAGMutation; |
33 | class CallLowering; |
34 | class GlobalValue; |
35 | class InlineAsmLowering; |
36 | class InstrItineraryData; |
37 | struct InstrStage; |
38 | class InstructionSelector; |
39 | class LegalizerInfo; |
40 | class MachineInstr; |
41 | struct MachineSchedPolicy; |
42 | struct MCReadAdvanceEntry; |
43 | struct MCWriteLatencyEntry; |
44 | struct MCWriteProcResEntry; |
45 | class RegisterBankInfo; |
46 | class SDep; |
47 | class SelectionDAGTargetInfo; |
48 | class SUnit; |
49 | class TargetFrameLowering; |
50 | class TargetInstrInfo; |
51 | class TargetLowering; |
52 | class TargetRegisterClass; |
53 | class TargetRegisterInfo; |
54 | class TargetSchedModel; |
55 | class Triple; |
56 | |
57 | //===----------------------------------------------------------------------===// |
58 | /// |
59 | /// TargetSubtargetInfo - Generic base class for all target subtargets. All |
60 | /// Target-specific options that control code generation and printing should |
61 | /// be exposed through a TargetSubtargetInfo-derived class. |
62 | /// |
63 | class TargetSubtargetInfo : public MCSubtargetInfo { |
64 | protected: // Can only create subclasses... |
65 | TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, |
66 | StringRef FS, ArrayRef<SubtargetFeatureKV> PF, |
67 | ArrayRef<SubtargetSubTypeKV> PD, |
68 | const MCWriteProcResEntry *WPR, |
69 | const MCWriteLatencyEntry *WL, |
70 | const MCReadAdvanceEntry *RA, const InstrStage *IS, |
71 | const unsigned *OC, const unsigned *FP); |
72 | |
73 | public: |
74 | // AntiDepBreakMode - Type of anti-dependence breaking that should |
75 | // be performed before post-RA scheduling. |
76 | using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL }; |
77 | using RegClassVector = SmallVectorImpl<const TargetRegisterClass *>; |
78 | |
79 | TargetSubtargetInfo() = delete; |
80 | TargetSubtargetInfo(const TargetSubtargetInfo &) = delete; |
81 | TargetSubtargetInfo &operator=(const TargetSubtargetInfo &) = delete; |
82 | ~TargetSubtargetInfo() override; |
83 | |
84 | virtual bool isXRaySupported() const { return false; } |
85 | |
86 | // Interfaces to the major aspects of target machine information: |
87 | // |
88 | // -- Instruction opcode and operand information |
89 | // -- Pipelines and scheduling information |
90 | // -- Stack frame information |
91 | // -- Selection DAG lowering information |
92 | // -- Call lowering information |
93 | // |
94 | // N.B. These objects may change during compilation. It's not safe to cache |
95 | // them between functions. |
96 | virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; } |
97 | virtual const TargetFrameLowering *getFrameLowering() const { |
98 | return nullptr; |
99 | } |
100 | virtual const TargetLowering *getTargetLowering() const { return nullptr; } |
101 | virtual const SelectionDAGTargetInfo *getSelectionDAGInfo() const { |
102 | return nullptr; |
103 | } |
104 | virtual const CallLowering *getCallLowering() const { return nullptr; } |
105 | |
106 | virtual const InlineAsmLowering *getInlineAsmLowering() const { |
107 | return nullptr; |
108 | } |
109 | |
110 | // FIXME: This lets targets specialize the selector by subtarget (which lets |
111 | // us do things like a dedicated avx512 selector). However, we might want |
112 | // to also specialize selectors by MachineFunction, which would let us be |
113 | // aware of optsize/optnone and such. |
114 | virtual InstructionSelector *getInstructionSelector() const { |
115 | return nullptr; |
116 | } |
117 | |
118 | /// Target can subclass this hook to select a different DAG scheduler. |
119 | virtual RegisterScheduler::FunctionPassCtor |
120 | getDAGScheduler(CodeGenOptLevel) const { |
121 | return nullptr; |
122 | } |
123 | |
124 | virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; } |
125 | |
126 | /// getRegisterInfo - If register information is available, return it. If |
127 | /// not, return null. |
128 | virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; } |
129 | |
130 | /// If the information for the register banks is available, return it. |
131 | /// Otherwise return nullptr. |
132 | virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; } |
133 | |
134 | /// getInstrItineraryData - Returns instruction itinerary data for the target |
135 | /// or specific subtarget. |
136 | virtual const InstrItineraryData *getInstrItineraryData() const { |
137 | return nullptr; |
138 | } |
139 | |
140 | /// Resolve a SchedClass at runtime, where SchedClass identifies an |
141 | /// MCSchedClassDesc with the isVariant property. This may return the ID of |
142 | /// another variant SchedClass, but repeated invocation must quickly terminate |
143 | /// in a nonvariant SchedClass. |
144 | virtual unsigned resolveSchedClass(unsigned SchedClass, |
145 | const MachineInstr *MI, |
146 | const TargetSchedModel *SchedModel) const { |
147 | return 0; |
148 | } |
149 | |
150 | /// Returns true if MI is a dependency breaking zero-idiom instruction for the |
151 | /// subtarget. |
152 | /// |
153 | /// This function also sets bits in Mask related to input operands that |
154 | /// are not in a data dependency relationship. There is one bit for each |
155 | /// machine operand; implicit operands follow explicit operands in the bit |
156 | /// representation used for Mask. An empty (i.e. a mask with all bits |
157 | /// cleared) means: data dependencies are "broken" for all the explicit input |
158 | /// machine operands of MI. |
159 | virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const { |
160 | return false; |
161 | } |
162 | |
163 | /// Returns true if MI is a dependency breaking instruction for the subtarget. |
164 | /// |
165 | /// Similar in behavior to `isZeroIdiom`. However, it knows how to identify |
166 | /// all dependency breaking instructions (i.e. not just zero-idioms). |
167 | /// |
168 | /// As for `isZeroIdiom`, this method returns a mask of "broken" dependencies. |
169 | /// (See method `isZeroIdiom` for a detailed description of Mask). |
170 | virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const { |
171 | return isZeroIdiom(MI, Mask); |
172 | } |
173 | |
174 | /// Returns true if MI is a candidate for move elimination. |
175 | /// |
176 | /// A candidate for move elimination may be optimized out at register renaming |
177 | /// stage. Subtargets can specify the set of optimizable moves by |
178 | /// instantiating tablegen class `IsOptimizableRegisterMove` (see |
179 | /// llvm/Target/TargetInstrPredicate.td). |
180 | /// |
181 | /// SubtargetEmitter is responsible for processing all the definitions of class |
182 | /// IsOptimizableRegisterMove, and auto-generate an override for this method. |
183 | virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const { |
184 | return false; |
185 | } |
186 | |
187 | /// True if the subtarget should run MachineScheduler after aggressive |
188 | /// coalescing. |
189 | /// |
190 | /// This currently replaces the SelectionDAG scheduler with the "source" order |
191 | /// scheduler (though see below for an option to turn this off and use the |
192 | /// TargetLowering preference). It does not yet disable the postRA scheduler. |
193 | virtual bool enableMachineScheduler() const; |
194 | |
195 | /// True if the machine scheduler should disable the TLI preference |
196 | /// for preRA scheduling with the source level scheduler. |
197 | virtual bool enableMachineSchedDefaultSched() const { return true; } |
198 | |
199 | /// True if the subtarget should run MachinePipeliner |
200 | virtual bool enableMachinePipeliner() const { return true; }; |
201 | |
202 | /// True if the subtarget should enable joining global copies. |
203 | /// |
204 | /// By default this is enabled if the machine scheduler is enabled, but |
205 | /// can be overridden. |
206 | virtual bool enableJoinGlobalCopies() const; |
207 | |
208 | /// True if the subtarget should run a scheduler after register allocation. |
209 | /// |
210 | /// By default this queries the PostRAScheduling bit in the scheduling model |
211 | /// which is the preferred way to influence this. |
212 | virtual bool enablePostRAScheduler() const; |
213 | |
214 | /// True if the subtarget should run a machine scheduler after register |
215 | /// allocation. |
216 | virtual bool enablePostRAMachineScheduler() const; |
217 | |
218 | /// True if the subtarget should run the atomic expansion pass. |
219 | virtual bool enableAtomicExpand() const; |
220 | |
221 | /// True if the subtarget should run the indirectbr expansion pass. |
222 | virtual bool enableIndirectBrExpand() const; |
223 | |
224 | /// Override generic scheduling policy within a region. |
225 | /// |
226 | /// This is a convenient way for targets that don't provide any custom |
227 | /// scheduling heuristics (no custom MachineSchedStrategy) to make |
228 | /// changes to the generic scheduling policy. |
229 | virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, |
230 | unsigned NumRegionInstrs) const {} |
231 | |
232 | // Perform target-specific adjustments to the latency of a schedule |
233 | // dependency. |
234 | // If a pair of operands is associated with the schedule dependency, DefOpIdx |
235 | // and UseOpIdx are the indices of the operands in Def and Use, respectively. |
236 | // Otherwise, either may be -1. |
237 | virtual void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, |
238 | int UseOpIdx, SDep &Dep, |
239 | const TargetSchedModel *SchedModel) const { |
240 | } |
241 | |
242 | // For use with PostRAScheduling: get the anti-dependence breaking that should |
243 | // be performed before post-RA scheduling. |
244 | virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; } |
245 | |
246 | // For use with PostRAScheduling: in CriticalPathRCs, return any register |
247 | // classes that should only be considered for anti-dependence breaking if they |
248 | // are on the critical path. |
249 | virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { |
250 | return CriticalPathRCs.clear(); |
251 | } |
252 | |
253 | // Provide an ordered list of schedule DAG mutations for the post-RA |
254 | // scheduler. |
255 | virtual void getPostRAMutations( |
256 | std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const { |
257 | } |
258 | |
259 | // Provide an ordered list of schedule DAG mutations for the machine |
260 | // pipeliner. |
261 | virtual void getSMSMutations( |
262 | std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const { |
263 | } |
264 | |
265 | /// Default to DFA for resource management, return false when target will use |
266 | /// ProcResource in InstrSchedModel instead. |
267 | virtual bool useDFAforSMS() const { return true; } |
268 | |
269 | // For use with PostRAScheduling: get the minimum optimization level needed |
270 | // to enable post-RA scheduling. |
271 | virtual CodeGenOptLevel getOptLevelToEnablePostRAScheduler() const { |
272 | return CodeGenOptLevel::Default; |
273 | } |
274 | |
275 | /// True if the subtarget should run the local reassignment |
276 | /// heuristic of the register allocator. |
277 | /// This heuristic may be compile time intensive, \p OptLevel provides |
278 | /// a finer grain to tune the register allocator. |
279 | virtual bool enableRALocalReassignment(CodeGenOptLevel OptLevel) const; |
280 | |
281 | /// Enable use of alias analysis during code generation (during MI |
282 | /// scheduling, DAGCombine, etc.). |
283 | virtual bool useAA() const; |
284 | |
285 | /// \brief Sink addresses into blocks using GEP instructions rather than |
286 | /// pointer casts and arithmetic. |
287 | virtual bool addrSinkUsingGEPs() const { |
288 | return useAA(); |
289 | } |
290 | |
291 | /// Enable the use of the early if conversion pass. |
292 | virtual bool enableEarlyIfConversion() const { return false; } |
293 | |
294 | /// Return PBQPConstraint(s) for the target. |
295 | /// |
296 | /// Override to provide custom PBQP constraints. |
297 | virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const { |
298 | return nullptr; |
299 | } |
300 | |
301 | /// Enable tracking of subregister liveness in register allocator. |
302 | /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where |
303 | /// possible. |
304 | virtual bool enableSubRegLiveness() const { return false; } |
305 | |
306 | /// This is called after a .mir file was loaded. |
307 | virtual void mirFileLoaded(MachineFunction &MF) const; |
308 | |
309 | /// True if the register allocator should use the allocation orders exactly as |
310 | /// written in the tablegen descriptions, false if it should allocate |
311 | /// the specified physical register later if is it callee-saved. |
312 | virtual bool ignoreCSRForAllocationOrder(const MachineFunction &MF, |
313 | unsigned PhysReg) const { |
314 | return false; |
315 | } |
316 | |
317 | /// Classify a global function reference. This mainly used to fetch target |
318 | /// special flags for lowering a function address. For example mark a function |
319 | /// call should be plt or pc-related addressing. |
320 | virtual unsigned char |
321 | classifyGlobalFunctionReference(const GlobalValue *GV) const { |
322 | return 0; |
323 | } |
324 | |
325 | /// Enable spillage copy elimination in MachineCopyPropagation pass. This |
326 | /// helps removing redundant copies generated by register allocator when |
327 | /// handling complex eviction chains. |
328 | virtual bool enableSpillageCopyElimination() const { return false; } |
329 | |
330 | /// Get the list of MacroFusion predicates. |
331 | virtual std::vector<MacroFusionPredTy> getMacroFusions() const { return {}; }; |
332 | |
333 | /// supportsInitUndef is used to determine if an architecture supports |
334 | /// the Init Undef Pass. By default, it is assumed that it will not support |
335 | /// the pass, with architecture specific overrides providing the information |
336 | /// where they are implemented. |
337 | virtual bool supportsInitUndef() const { return false; } |
338 | }; |
339 | |
340 | } // end namespace llvm |
341 | |
342 | #endif // LLVM_CODEGEN_TARGETSUBTARGETINFO_H |
343 | |