1//===- ARMFastISel.cpp - ARM FastISel implementation ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the ARM-specific support for the FastISel class. Some
10// of the target-specific code is generated by tablegen in the file
11// ARMGenFastISel.inc, which is #included here.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMConstantPoolValue.h"
20#include "ARMISelLowering.h"
21#include "ARMMachineFunctionInfo.h"
22#include "ARMSubtarget.h"
23#include "MCTargetDesc/ARMAddressingModes.h"
24#include "MCTargetDesc/ARMBaseInfo.h"
25#include "Utils/ARMBaseInfo.h"
26#include "llvm/ADT/APFloat.h"
27#include "llvm/ADT/APInt.h"
28#include "llvm/ADT/DenseMap.h"
29#include "llvm/ADT/SmallVector.h"
30#include "llvm/CodeGen/CallingConvLower.h"
31#include "llvm/CodeGen/FastISel.h"
32#include "llvm/CodeGen/FunctionLoweringInfo.h"
33#include "llvm/CodeGen/ISDOpcodes.h"
34#include "llvm/CodeGen/MachineBasicBlock.h"
35#include "llvm/CodeGen/MachineConstantPool.h"
36#include "llvm/CodeGen/MachineFrameInfo.h"
37#include "llvm/CodeGen/MachineFunction.h"
38#include "llvm/CodeGen/MachineInstr.h"
39#include "llvm/CodeGen/MachineInstrBuilder.h"
40#include "llvm/CodeGen/MachineMemOperand.h"
41#include "llvm/CodeGen/MachineOperand.h"
42#include "llvm/CodeGen/MachineRegisterInfo.h"
43#include "llvm/CodeGen/TargetInstrInfo.h"
44#include "llvm/CodeGen/TargetLowering.h"
45#include "llvm/CodeGen/TargetOpcodes.h"
46#include "llvm/CodeGen/TargetRegisterInfo.h"
47#include "llvm/CodeGen/ValueTypes.h"
48#include "llvm/CodeGenTypes/MachineValueType.h"
49#include "llvm/IR/Argument.h"
50#include "llvm/IR/Attributes.h"
51#include "llvm/IR/CallingConv.h"
52#include "llvm/IR/Constant.h"
53#include "llvm/IR/Constants.h"
54#include "llvm/IR/DataLayout.h"
55#include "llvm/IR/DerivedTypes.h"
56#include "llvm/IR/Function.h"
57#include "llvm/IR/GetElementPtrTypeIterator.h"
58#include "llvm/IR/GlobalValue.h"
59#include "llvm/IR/GlobalVariable.h"
60#include "llvm/IR/InstrTypes.h"
61#include "llvm/IR/Instruction.h"
62#include "llvm/IR/Instructions.h"
63#include "llvm/IR/IntrinsicInst.h"
64#include "llvm/IR/Intrinsics.h"
65#include "llvm/IR/Module.h"
66#include "llvm/IR/Operator.h"
67#include "llvm/IR/Type.h"
68#include "llvm/IR/User.h"
69#include "llvm/IR/Value.h"
70#include "llvm/MC/MCInstrDesc.h"
71#include "llvm/Support/Casting.h"
72#include "llvm/Support/Compiler.h"
73#include "llvm/Support/ErrorHandling.h"
74#include "llvm/Support/MathExtras.h"
75#include "llvm/Target/TargetMachine.h"
76#include "llvm/Target/TargetOptions.h"
77#include <cassert>
78#include <cstdint>
79#include <utility>
80
81using namespace llvm;
82
83namespace {
84
85 // All possible address modes, plus some.
86class Address {
87public:
88 using BaseKind = enum { RegBase, FrameIndexBase };
89
90private:
91 BaseKind Kind = RegBase;
92 union {
93 unsigned Reg;
94 int FI;
95 } Base;
96
97 int Offset = 0;
98
99public:
100 // Innocuous defaults for our address.
101 Address() { Base.Reg = 0; }
102
103 void setKind(BaseKind K) { Kind = K; }
104 BaseKind getKind() const { return Kind; }
105 bool isRegBase() const { return Kind == RegBase; }
106 bool isFIBase() const { return Kind == FrameIndexBase; }
107
108 void setReg(Register Reg) {
109 assert(isRegBase() && "Invalid base register access!");
110 Base.Reg = Reg.id();
111 }
112
113 Register getReg() const {
114 assert(isRegBase() && "Invalid base register access!");
115 return Base.Reg;
116 }
117
118 void setFI(int FI) {
119 assert(isFIBase() && "Invalid base frame index access!");
120 Base.FI = FI;
121 }
122
123 int getFI() const {
124 assert(isFIBase() && "Invalid base frame index access!");
125 return Base.FI;
126 }
127
128 void setOffset(int O) { Offset = O; }
129 int getOffset() { return Offset; }
130};
131
132class ARMFastISel final : public FastISel {
133 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
134 /// make the right decision when generating code for different targets.
135 const ARMSubtarget *Subtarget;
136 Module &M;
137 const TargetMachine &TM;
138 const TargetInstrInfo &TII;
139 const TargetLowering &TLI;
140 ARMFunctionInfo *AFI;
141
142 // Convenience variables to avoid some queries.
143 bool isThumb2;
144 LLVMContext *Context;
145
146 public:
147 explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
148 const TargetLibraryInfo *libInfo)
149 : FastISel(funcInfo, libInfo),
150 Subtarget(&funcInfo.MF->getSubtarget<ARMSubtarget>()),
151 M(const_cast<Module &>(*funcInfo.Fn->getParent())),
152 TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()),
153 TLI(*Subtarget->getTargetLowering()) {
154 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
155 isThumb2 = AFI->isThumbFunction();
156 Context = &funcInfo.Fn->getContext();
157 }
158
159 private:
160 // Code from FastISel.cpp.
161
162 Register fastEmitInst_r(unsigned MachineInstOpcode,
163 const TargetRegisterClass *RC, Register Op0);
164 Register fastEmitInst_rr(unsigned MachineInstOpcode,
165 const TargetRegisterClass *RC, Register Op0,
166 Register Op1);
167 Register fastEmitInst_ri(unsigned MachineInstOpcode,
168 const TargetRegisterClass *RC, Register Op0,
169 uint64_t Imm);
170 Register fastEmitInst_i(unsigned MachineInstOpcode,
171 const TargetRegisterClass *RC, uint64_t Imm);
172
173 // Backend specific FastISel code.
174
175 bool fastSelectInstruction(const Instruction *I) override;
176 Register fastMaterializeConstant(const Constant *C) override;
177 Register fastMaterializeAlloca(const AllocaInst *AI) override;
178 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
179 const LoadInst *LI) override;
180 bool fastLowerArguments() override;
181
182#include "ARMGenFastISel.inc"
183
184 // Instruction selection routines.
185
186 bool SelectLoad(const Instruction *I);
187 bool SelectStore(const Instruction *I);
188 bool SelectBranch(const Instruction *I);
189 bool SelectIndirectBr(const Instruction *I);
190 bool SelectCmp(const Instruction *I);
191 bool SelectFPExt(const Instruction *I);
192 bool SelectFPTrunc(const Instruction *I);
193 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
194 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
195 bool SelectIToFP(const Instruction *I, bool isSigned);
196 bool SelectFPToI(const Instruction *I, bool isSigned);
197 bool SelectDiv(const Instruction *I, bool isSigned);
198 bool SelectRem(const Instruction *I, bool isSigned);
199 bool SelectCall(const Instruction *I, const char *IntrMemName);
200 bool SelectIntrinsicCall(const IntrinsicInst &I);
201 bool SelectSelect(const Instruction *I);
202 bool SelectRet(const Instruction *I);
203 bool SelectTrunc(const Instruction *I);
204 bool SelectIntExt(const Instruction *I);
205 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
206
207 // Utility routines.
208
209 bool isPositionIndependent() const;
210 bool isTypeLegal(Type *Ty, MVT &VT);
211 bool isLoadTypeLegal(Type *Ty, MVT &VT);
212 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
213 bool isZExt);
214 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
215 MaybeAlign Alignment = std::nullopt, bool isZExt = true,
216 bool allocReg = true);
217 bool ARMEmitStore(MVT VT, Register SrcReg, Address &Addr,
218 MaybeAlign Alignment = std::nullopt);
219 bool ARMComputeAddress(const Value *Obj, Address &Addr);
220 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
221 bool ARMIsMemCpySmall(uint64_t Len);
222 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
223 MaybeAlign Alignment);
224 Register ARMEmitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT, bool isZExt);
225 Register ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
226 Register ARMMaterializeInt(const Constant *C, MVT VT);
227 Register ARMMaterializeGV(const GlobalValue *GV, MVT VT);
228 Register ARMMoveToFPReg(MVT VT, Register SrcReg);
229 Register ARMMoveToIntReg(MVT VT, Register SrcReg);
230 unsigned ARMSelectCallOp(bool UseReg);
231 Register ARMLowerPICELF(const GlobalValue *GV, MVT VT);
232
233 const TargetLowering *getTargetLowering() { return &TLI; }
234
235 // Call handling routines.
236
237 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
238 bool Return,
239 bool isVarArg);
240 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
241 SmallVectorImpl<Register> &ArgRegs,
242 SmallVectorImpl<MVT> &ArgVTs,
243 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
244 SmallVectorImpl<Register> &RegArgs,
245 CallingConv::ID CC,
246 unsigned &NumBytes,
247 bool isVarArg);
248 Register getLibcallReg(const Twine &Name);
249 bool FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
250 const Instruction *I, CallingConv::ID CC,
251 unsigned &NumBytes, bool isVarArg);
252 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
253
254 // OptionalDef handling routines.
255
256 bool isARMNEONPred(const MachineInstr *MI);
257 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
258 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
259 void AddLoadStoreOperands(MVT VT, Address &Addr,
260 const MachineInstrBuilder &MIB,
261 MachineMemOperand::Flags Flags, bool useAM3);
262};
263
264} // end anonymous namespace
265
266// DefinesOptionalPredicate - This is different from DefinesPredicate in that
267// we don't care about implicit defs here, just places we'll need to add a
268// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
269bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
270 if (!MI->hasOptionalDef())
271 return false;
272
273 // Look to see if our OptionalDef is defining CPSR or CCR.
274 for (const MachineOperand &MO : MI->operands()) {
275 if (!MO.isReg() || !MO.isDef()) continue;
276 if (MO.getReg() == ARM::CPSR)
277 *CPSR = true;
278 }
279 return true;
280}
281
282bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
283 const MCInstrDesc &MCID = MI->getDesc();
284
285 // If we're a thumb2 or not NEON function we'll be handled via isPredicable.
286 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
287 AFI->isThumb2Function())
288 return MI->isPredicable();
289
290 for (const MCOperandInfo &opInfo : MCID.operands())
291 if (opInfo.isPredicate())
292 return true;
293
294 return false;
295}
296
297// If the machine is predicable go ahead and add the predicate operands, if
298// it needs default CC operands add those.
299// TODO: If we want to support thumb1 then we'll need to deal with optional
300// CPSR defs that need to be added before the remaining operands. See s_cc_out
301// for descriptions why.
302const MachineInstrBuilder &
303ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
304 MachineInstr *MI = &*MIB;
305
306 // Do we use a predicate? or...
307 // Are we NEON in ARM mode and have a predicate operand? If so, I know
308 // we're not predicable but add it anyways.
309 if (isARMNEONPred(MI))
310 MIB.add(MOs: predOps(Pred: ARMCC::AL));
311
312 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
313 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
314 bool CPSR = false;
315 if (DefinesOptionalPredicate(MI, CPSR: &CPSR))
316 MIB.add(MO: CPSR ? t1CondCodeOp() : condCodeOp());
317 return MIB;
318}
319
320Register ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
321 const TargetRegisterClass *RC,
322 Register Op0) {
323 Register ResultReg = createResultReg(RC);
324 const MCInstrDesc &II = TII.get(Opcode: MachineInstOpcode);
325
326 // Make sure the input operand is sufficiently constrained to be legal
327 // for this instruction.
328 Op0 = constrainOperandRegClass(II, Op: Op0, OpNum: 1);
329 if (II.getNumDefs() >= 1) {
330 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II,
331 DestReg: ResultReg).addReg(RegNo: Op0));
332 } else {
333 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II)
334 .addReg(RegNo: Op0));
335 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
336 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: ResultReg)
337 .addReg(RegNo: II.implicit_defs()[0]));
338 }
339 return ResultReg;
340}
341
342Register ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
343 const TargetRegisterClass *RC,
344 Register Op0, Register Op1) {
345 Register ResultReg = createResultReg(RC);
346 const MCInstrDesc &II = TII.get(Opcode: MachineInstOpcode);
347
348 // Make sure the input operands are sufficiently constrained to be legal
349 // for this instruction.
350 Op0 = constrainOperandRegClass(II, Op: Op0, OpNum: 1);
351 Op1 = constrainOperandRegClass(II, Op: Op1, OpNum: 2);
352
353 if (II.getNumDefs() >= 1) {
354 AddOptionalDefs(
355 MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II, DestReg: ResultReg)
356 .addReg(RegNo: Op0)
357 .addReg(RegNo: Op1));
358 } else {
359 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II)
360 .addReg(RegNo: Op0)
361 .addReg(RegNo: Op1));
362 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
363 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: ResultReg)
364 .addReg(RegNo: II.implicit_defs()[0]));
365 }
366 return ResultReg;
367}
368
369Register ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
370 const TargetRegisterClass *RC,
371 Register Op0, uint64_t Imm) {
372 Register ResultReg = createResultReg(RC);
373 const MCInstrDesc &II = TII.get(Opcode: MachineInstOpcode);
374
375 // Make sure the input operand is sufficiently constrained to be legal
376 // for this instruction.
377 Op0 = constrainOperandRegClass(II, Op: Op0, OpNum: 1);
378 if (II.getNumDefs() >= 1) {
379 AddOptionalDefs(
380 MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II, DestReg: ResultReg)
381 .addReg(RegNo: Op0)
382 .addImm(Val: Imm));
383 } else {
384 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II)
385 .addReg(RegNo: Op0)
386 .addImm(Val: Imm));
387 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
388 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: ResultReg)
389 .addReg(RegNo: II.implicit_defs()[0]));
390 }
391 return ResultReg;
392}
393
394Register ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
395 const TargetRegisterClass *RC,
396 uint64_t Imm) {
397 Register ResultReg = createResultReg(RC);
398 const MCInstrDesc &II = TII.get(Opcode: MachineInstOpcode);
399
400 if (II.getNumDefs() >= 1) {
401 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II,
402 DestReg: ResultReg).addImm(Val: Imm));
403 } else {
404 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II)
405 .addImm(Val: Imm));
406 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
407 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: ResultReg)
408 .addReg(RegNo: II.implicit_defs()[0]));
409 }
410 return ResultReg;
411}
412
413// TODO: Don't worry about 64-bit now, but when this is fixed remove the
414// checks from the various callers.
415Register ARMFastISel::ARMMoveToFPReg(MVT VT, Register SrcReg) {
416 if (VT == MVT::f64)
417 return Register();
418
419 Register MoveReg = createResultReg(RC: TLI.getRegClassFor(VT));
420 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
421 MCID: TII.get(Opcode: ARM::VMOVSR), DestReg: MoveReg)
422 .addReg(RegNo: SrcReg));
423 return MoveReg;
424}
425
426Register ARMFastISel::ARMMoveToIntReg(MVT VT, Register SrcReg) {
427 if (VT == MVT::i64)
428 return Register();
429
430 Register MoveReg = createResultReg(RC: TLI.getRegClassFor(VT));
431 AddOptionalDefs(MIB: BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
432 TII.get(ARM::Opcode: VMOVRS), MoveReg)
433 .addReg(SrcReg));
434 return MoveReg;
435}
436
437// For double width floating point we need to materialize two constants
438// (the high and the low) into integer registers then use a move to get
439// the combined constant into an FP reg.
440Register ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
441 const APFloat Val = CFP->getValueAPF();
442 bool is64bit = VT == MVT::f64;
443
444 // This checks to see if we can use VFP3 instructions to materialize
445 // a constant, otherwise we have to go through the constant pool.
446 if (TLI.isFPImmLegal(Val, VT)) {
447 int Imm;
448 unsigned Opc;
449 if (is64bit) {
450 Imm = ARM_AM::getFP64Imm(FPImm: Val);
451 Opc = ARM::FCONSTD;
452 } else {
453 Imm = ARM_AM::getFP32Imm(FPImm: Val);
454 Opc = ARM::FCONSTS;
455 }
456 Register DestReg = createResultReg(RC: TLI.getRegClassFor(VT));
457 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
458 MCID: TII.get(Opcode: Opc), DestReg).addImm(Val: Imm));
459 return DestReg;
460 }
461
462 // Require VFP2 for loading fp constants.
463 if (!Subtarget->hasVFP2Base()) return false;
464
465 // MachineConstantPool wants an explicit alignment.
466 Align Alignment = DL.getPrefTypeAlign(Ty: CFP->getType());
467 unsigned Idx = MCP.getConstantPoolIndex(C: cast<Constant>(Val: CFP), Alignment);
468 Register DestReg = createResultReg(RC: TLI.getRegClassFor(VT));
469 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
470
471 // The extra reg is for addrmode5.
472 AddOptionalDefs(
473 MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg)
474 .addConstantPoolIndex(Idx)
475 .addReg(RegNo: 0));
476 return DestReg;
477}
478
479Register ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
480 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
481 return Register();
482
483 // If we can do this in a single instruction without a constant pool entry
484 // do so now.
485 const ConstantInt *CI = cast<ConstantInt>(Val: C);
486 if (Subtarget->hasV6T2Ops() && isUInt<16>(x: CI->getZExtValue())) {
487 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
488 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
489 &ARM::GPRRegClass;
490 Register ImmReg = createResultReg(RC);
491 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
492 MCID: TII.get(Opcode: Opc), DestReg: ImmReg)
493 .addImm(Val: CI->getZExtValue()));
494 return ImmReg;
495 }
496
497 // Use MVN to emit negative constants.
498 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
499 unsigned Imm = (unsigned)~(CI->getSExtValue());
500 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Arg: Imm) != -1) :
501 (ARM_AM::getSOImmVal(Arg: Imm) != -1);
502 if (UseImm) {
503 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
504 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
505 &ARM::GPRRegClass;
506 Register ImmReg = createResultReg(RC);
507 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
508 MCID: TII.get(Opcode: Opc), DestReg: ImmReg)
509 .addImm(Val: Imm));
510 return ImmReg;
511 }
512 }
513
514 Register ResultReg;
515 if (Subtarget->useMovt())
516 ResultReg = fastEmit_i(VT, RetVT: VT, Opcode: ISD::Constant, Imm: CI->getZExtValue());
517
518 if (ResultReg)
519 return ResultReg;
520
521 // Load from constant pool. For now 32-bit only.
522 if (VT != MVT::i32)
523 return Register();
524
525 // MachineConstantPool wants an explicit alignment.
526 Align Alignment = DL.getPrefTypeAlign(Ty: C->getType());
527 unsigned Idx = MCP.getConstantPoolIndex(C, Alignment);
528 ResultReg = createResultReg(RC: TLI.getRegClassFor(VT));
529 if (isThumb2)
530 AddOptionalDefs(MIB: BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
531 TII.get(ARM::Opcode: t2LDRpci), ResultReg)
532 .addConstantPoolIndex(Idx));
533 else {
534 // The extra immediate is for addrmode2.
535 ResultReg = constrainOperandRegClass(II: TII.get(ARM::Opcode: LDRcp), Op: ResultReg, OpNum: 0);
536 AddOptionalDefs(MIB: BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
537 TII.get(ARM::Opcode: LDRcp), ResultReg)
538 .addConstantPoolIndex(Idx)
539 .addImm(0));
540 }
541 return ResultReg;
542}
543
544bool ARMFastISel::isPositionIndependent() const {
545 return TLI.isPositionIndependent();
546}
547
548Register ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
549 // For now 32-bit only.
550 if (VT != MVT::i32 || GV->isThreadLocal())
551 return Register();
552
553 // ROPI/RWPI not currently supported.
554 if (Subtarget->isROPI() || Subtarget->isRWPI())
555 return Register();
556
557 bool IsIndirect = Subtarget->isGVIndirectSymbol(GV);
558 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
559 : &ARM::GPRRegClass;
560 Register DestReg = createResultReg(RC);
561
562 // FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
563 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(Val: GV);
564 bool IsThreadLocal = GVar && GVar->isThreadLocal();
565 if (!Subtarget->isTargetMachO() && IsThreadLocal)
566 return Register();
567
568 bool IsPositionIndependent = isPositionIndependent();
569 // Use movw+movt when possible, it avoids constant pool entries.
570 // Non-darwin targets only support static movt relocations in FastISel.
571 if (Subtarget->useMovt() &&
572 (Subtarget->isTargetMachO() || !IsPositionIndependent)) {
573 unsigned Opc;
574 unsigned char TF = 0;
575 if (Subtarget->isTargetMachO())
576 TF = ARMII::MO_NONLAZY;
577
578 if (IsPositionIndependent)
579 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
580 else
581 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
582 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
583 MCID: TII.get(Opcode: Opc), DestReg).addGlobalAddress(GV, Offset: 0, TargetFlags: TF));
584 } else {
585 // MachineConstantPool wants an explicit alignment.
586 Align Alignment = DL.getPrefTypeAlign(Ty: GV->getType());
587
588 if (Subtarget->isTargetELF() && IsPositionIndependent)
589 return ARMLowerPICELF(GV, VT);
590
591 // Grab index.
592 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
593 unsigned Id = AFI->createPICLabelUId();
594 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(C: GV, ID: Id,
595 Kind: ARMCP::CPValue,
596 PCAdj);
597 unsigned Idx = MCP.getConstantPoolIndex(V: CPV, Alignment);
598
599 // Load value.
600 MachineInstrBuilder MIB;
601 if (isThumb2) {
602 unsigned Opc = IsPositionIndependent ? ARM::t2LDRpci_pic : ARM::t2LDRpci;
603 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc),
604 DestReg).addConstantPoolIndex(Idx);
605 if (IsPositionIndependent)
606 MIB.addImm(Val: Id);
607 AddOptionalDefs(MIB);
608 } else {
609 // The extra immediate is for addrmode2.
610 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
611 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
612 TII.get(ARM::LDRcp), DestReg)
613 .addConstantPoolIndex(Idx)
614 .addImm(0);
615 AddOptionalDefs(MIB);
616
617 if (IsPositionIndependent) {
618 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
619 Register NewDestReg = createResultReg(RC: TLI.getRegClassFor(VT));
620
621 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt,
622 MIMD, MCID: TII.get(Opcode: Opc), DestReg: NewDestReg)
623 .addReg(RegNo: DestReg)
624 .addImm(Val: Id);
625 AddOptionalDefs(MIB);
626 return NewDestReg;
627 }
628 }
629 }
630
631 if ((Subtarget->isTargetELF() && Subtarget->isGVInGOT(GV)) ||
632 (Subtarget->isTargetMachO() && IsIndirect)) {
633 MachineInstrBuilder MIB;
634 Register NewDestReg = createResultReg(RC: TLI.getRegClassFor(VT));
635 if (isThumb2)
636 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
637 TII.get(ARM::t2LDRi12), NewDestReg)
638 .addReg(DestReg)
639 .addImm(0);
640 else
641 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
642 TII.get(ARM::LDRi12), NewDestReg)
643 .addReg(DestReg)
644 .addImm(0);
645 DestReg = NewDestReg;
646 AddOptionalDefs(MIB);
647 }
648
649 return DestReg;
650}
651
652Register ARMFastISel::fastMaterializeConstant(const Constant *C) {
653 EVT CEVT = TLI.getValueType(DL, Ty: C->getType(), AllowUnknown: true);
654
655 // Only handle simple types.
656 if (!CEVT.isSimple())
657 return Register();
658 MVT VT = CEVT.getSimpleVT();
659
660 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Val: C))
661 return ARMMaterializeFP(CFP, VT);
662 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(Val: C))
663 return ARMMaterializeGV(GV, VT);
664 else if (isa<ConstantInt>(Val: C))
665 return ARMMaterializeInt(C, VT);
666
667 return Register();
668}
669
670// TODO: Register ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
671
672Register ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
673 // Don't handle dynamic allocas.
674 if (!FuncInfo.StaticAllocaMap.count(Val: AI))
675 return Register();
676
677 MVT VT;
678 if (!isLoadTypeLegal(Ty: AI->getType(), VT))
679 return Register();
680
681 DenseMap<const AllocaInst*, int>::iterator SI =
682 FuncInfo.StaticAllocaMap.find(Val: AI);
683
684 // This will get lowered later into the correct offsets and registers
685 // via rewriteXFrameIndex.
686 if (SI != FuncInfo.StaticAllocaMap.end()) {
687 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
688 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
689 Register ResultReg = createResultReg(RC);
690 ResultReg = constrainOperandRegClass(II: TII.get(Opcode: Opc), Op: ResultReg, OpNum: 0);
691
692 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
693 MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
694 .addFrameIndex(Idx: SI->second)
695 .addImm(Val: 0));
696 return ResultReg;
697 }
698
699 return Register();
700}
701
702bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
703 EVT evt = TLI.getValueType(DL, Ty, AllowUnknown: true);
704
705 // Only handle simple types.
706 if (evt == MVT::Other || !evt.isSimple()) return false;
707 VT = evt.getSimpleVT();
708
709 // Handle all legal types, i.e. a register that will directly hold this
710 // value.
711 return TLI.isTypeLegal(VT);
712}
713
714bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
715 if (isTypeLegal(Ty, VT)) return true;
716
717 // If this is a type than can be sign or zero-extended to a basic operation
718 // go ahead and accept it now.
719 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
720 return true;
721
722 return false;
723}
724
725// Computes the address to get to an object.
726bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
727 // Some boilerplate from the X86 FastISel.
728 const User *U = nullptr;
729 unsigned Opcode = Instruction::UserOp1;
730 if (const Instruction *I = dyn_cast<Instruction>(Val: Obj)) {
731 // Don't walk into other basic blocks unless the object is an alloca from
732 // another block, otherwise it may not have a virtual register assigned.
733 if (FuncInfo.StaticAllocaMap.count(Val: static_cast<const AllocaInst *>(Obj)) ||
734 FuncInfo.getMBB(BB: I->getParent()) == FuncInfo.MBB) {
735 Opcode = I->getOpcode();
736 U = I;
737 }
738 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Val: Obj)) {
739 Opcode = C->getOpcode();
740 U = C;
741 }
742
743 if (PointerType *Ty = dyn_cast<PointerType>(Val: Obj->getType()))
744 if (Ty->getAddressSpace() > 255)
745 // Fast instruction selection doesn't support the special
746 // address spaces.
747 return false;
748
749 switch (Opcode) {
750 default:
751 break;
752 case Instruction::BitCast:
753 // Look through bitcasts.
754 return ARMComputeAddress(Obj: U->getOperand(i: 0), Addr);
755 case Instruction::IntToPtr:
756 // Look past no-op inttoptrs.
757 if (TLI.getValueType(DL, Ty: U->getOperand(i: 0)->getType()) ==
758 TLI.getPointerTy(DL))
759 return ARMComputeAddress(Obj: U->getOperand(i: 0), Addr);
760 break;
761 case Instruction::PtrToInt:
762 // Look past no-op ptrtoints.
763 if (TLI.getValueType(DL, Ty: U->getType()) == TLI.getPointerTy(DL))
764 return ARMComputeAddress(Obj: U->getOperand(i: 0), Addr);
765 break;
766 case Instruction::GetElementPtr: {
767 Address SavedAddr = Addr;
768 int TmpOffset = Addr.getOffset();
769
770 // Iterate through the GEP folding the constants into offsets where
771 // we can.
772 gep_type_iterator GTI = gep_type_begin(GEP: U);
773 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
774 i != e; ++i, ++GTI) {
775 const Value *Op = *i;
776 if (StructType *STy = GTI.getStructTypeOrNull()) {
777 const StructLayout *SL = DL.getStructLayout(Ty: STy);
778 unsigned Idx = cast<ConstantInt>(Val: Op)->getZExtValue();
779 TmpOffset += SL->getElementOffset(Idx);
780 } else {
781 uint64_t S = GTI.getSequentialElementStride(DL);
782 while (true) {
783 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val: Op)) {
784 // Constant-offset addressing.
785 TmpOffset += CI->getSExtValue() * S;
786 break;
787 }
788 if (canFoldAddIntoGEP(GEP: U, Add: Op)) {
789 // A compatible add with a constant operand. Fold the constant.
790 ConstantInt *CI =
791 cast<ConstantInt>(Val: cast<AddOperator>(Val: Op)->getOperand(i_nocapture: 1));
792 TmpOffset += CI->getSExtValue() * S;
793 // Iterate on the other operand.
794 Op = cast<AddOperator>(Val: Op)->getOperand(i_nocapture: 0);
795 continue;
796 }
797 // Unsupported
798 goto unsupported_gep;
799 }
800 }
801 }
802
803 // Try to grab the base operand now.
804 Addr.setOffset(TmpOffset);
805 if (ARMComputeAddress(Obj: U->getOperand(i: 0), Addr)) return true;
806
807 // We failed, restore everything and try the other options.
808 Addr = SavedAddr;
809
810 unsupported_gep:
811 break;
812 }
813 case Instruction::Alloca: {
814 const AllocaInst *AI = cast<AllocaInst>(Val: Obj);
815 DenseMap<const AllocaInst*, int>::iterator SI =
816 FuncInfo.StaticAllocaMap.find(Val: AI);
817 if (SI != FuncInfo.StaticAllocaMap.end()) {
818 Addr.setKind(Address::FrameIndexBase);
819 Addr.setFI(SI->second);
820 return true;
821 }
822 break;
823 }
824 }
825
826 // Try to get this in a register if nothing else has worked.
827 if (!Addr.getReg())
828 Addr.setReg(getRegForValue(V: Obj));
829 return Addr.getReg();
830}
831
832void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
833 bool needsLowering = false;
834 switch (VT.SimpleTy) {
835 default: llvm_unreachable("Unhandled load/store type!");
836 case MVT::i1:
837 case MVT::i8:
838 case MVT::i16:
839 case MVT::i32:
840 if (!useAM3) {
841 // Integer loads/stores handle 12-bit offsets.
842 needsLowering = ((Addr.getOffset() & 0xfff) != Addr.getOffset());
843 // Handle negative offsets.
844 if (needsLowering && isThumb2)
845 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.getOffset() < 0 &&
846 Addr.getOffset() > -256);
847 } else {
848 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
849 needsLowering = (Addr.getOffset() > 255 || Addr.getOffset() < -255);
850 }
851 break;
852 case MVT::f32:
853 case MVT::f64:
854 // Floating point operands handle 8-bit offsets.
855 needsLowering = ((Addr.getOffset() & 0xff) != Addr.getOffset());
856 break;
857 }
858
859 // If this is a stack pointer and the offset needs to be simplified then
860 // put the alloca address into a register, set the base type back to
861 // register and continue. This should almost never happen.
862 if (needsLowering && Addr.isFIBase()) {
863 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
864 : &ARM::GPRRegClass;
865 Register ResultReg = createResultReg(RC);
866 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
867 AddOptionalDefs(
868 MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
869 .addFrameIndex(Idx: Addr.getFI())
870 .addImm(Val: 0));
871 Addr.setKind(Address::RegBase);
872 Addr.setReg(ResultReg);
873 }
874
875 // Since the offset is too large for the load/store instruction
876 // get the reg+offset into a register.
877 if (needsLowering) {
878 Addr.setReg(fastEmit_ri_(MVT::i32, ISD::ADD, Addr.getReg(),
879 Addr.getOffset(), MVT::i32));
880 Addr.setOffset(0);
881 }
882}
883
884void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
885 const MachineInstrBuilder &MIB,
886 MachineMemOperand::Flags Flags,
887 bool useAM3) {
888 // addrmode5 output depends on the selection dag addressing dividing the
889 // offset by 4 that it then later multiplies. Do this here as well.
890 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
891 Addr.setOffset(Addr.getOffset() / 4);
892
893 // Frame base works a bit differently. Handle it separately.
894 if (Addr.isFIBase()) {
895 int FI = Addr.getFI();
896 int Offset = Addr.getOffset();
897 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
898 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *FuncInfo.MF, FI, Offset), F: Flags,
899 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
900 // Now add the rest of the operands.
901 MIB.addFrameIndex(Idx: FI);
902
903 // ARM halfword load/stores and signed byte loads need an additional
904 // operand.
905 if (useAM3) {
906 int Imm = (Addr.getOffset() < 0) ? (0x100 | -Addr.getOffset())
907 : Addr.getOffset();
908 MIB.addReg(RegNo: 0);
909 MIB.addImm(Val: Imm);
910 } else {
911 MIB.addImm(Val: Addr.getOffset());
912 }
913 MIB.addMemOperand(MMO);
914 } else {
915 // Now add the rest of the operands.
916 MIB.addReg(RegNo: Addr.getReg());
917
918 // ARM halfword load/stores and signed byte loads need an additional
919 // operand.
920 if (useAM3) {
921 int Imm = (Addr.getOffset() < 0) ? (0x100 | -Addr.getOffset())
922 : Addr.getOffset();
923 MIB.addReg(RegNo: 0);
924 MIB.addImm(Val: Imm);
925 } else {
926 MIB.addImm(Val: Addr.getOffset());
927 }
928 }
929 AddOptionalDefs(MIB);
930}
931
932bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
933 MaybeAlign Alignment, bool isZExt,
934 bool allocReg) {
935 unsigned Opc;
936 bool useAM3 = false;
937 bool needVMOV = false;
938 const TargetRegisterClass *RC;
939 switch (VT.SimpleTy) {
940 // This is mostly going to be Neon/vector support.
941 default: return false;
942 case MVT::i1:
943 case MVT::i8:
944 if (isThumb2) {
945 if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
946 Subtarget->hasV6T2Ops())
947 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
948 else
949 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
950 } else {
951 if (isZExt) {
952 Opc = ARM::LDRBi12;
953 } else {
954 Opc = ARM::LDRSB;
955 useAM3 = true;
956 }
957 }
958 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
959 break;
960 case MVT::i16:
961 if (Alignment && *Alignment < Align(2) &&
962 !Subtarget->allowsUnalignedMem())
963 return false;
964
965 if (isThumb2) {
966 if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
967 Subtarget->hasV6T2Ops())
968 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
969 else
970 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
971 } else {
972 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
973 useAM3 = true;
974 }
975 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
976 break;
977 case MVT::i32:
978 if (Alignment && *Alignment < Align(4) &&
979 !Subtarget->allowsUnalignedMem())
980 return false;
981
982 if (isThumb2) {
983 if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
984 Subtarget->hasV6T2Ops())
985 Opc = ARM::t2LDRi8;
986 else
987 Opc = ARM::t2LDRi12;
988 } else {
989 Opc = ARM::LDRi12;
990 }
991 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
992 break;
993 case MVT::f32:
994 if (!Subtarget->hasVFP2Base()) return false;
995 // Unaligned loads need special handling. Floats require word-alignment.
996 if (Alignment && *Alignment < Align(4)) {
997 needVMOV = true;
998 VT = MVT::i32;
999 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1000 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1001 } else {
1002 Opc = ARM::VLDRS;
1003 RC = TLI.getRegClassFor(VT);
1004 }
1005 break;
1006 case MVT::f64:
1007 // Can load and store double precision even without FeatureFP64
1008 if (!Subtarget->hasVFP2Base()) return false;
1009 // FIXME: Unaligned loads need special handling. Doublewords require
1010 // word-alignment.
1011 if (Alignment && *Alignment < Align(4))
1012 return false;
1013
1014 Opc = ARM::VLDRD;
1015 RC = TLI.getRegClassFor(VT);
1016 break;
1017 }
1018 // Simplify this down to something we can handle.
1019 ARMSimplifyAddress(Addr, VT, useAM3);
1020
1021 // Create the base instruction, then add the operands.
1022 if (allocReg)
1023 ResultReg = createResultReg(RC);
1024 assert(ResultReg.isVirtual() && "Expected an allocated virtual register.");
1025 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1026 MCID: TII.get(Opcode: Opc), DestReg: ResultReg);
1027 AddLoadStoreOperands(VT, Addr, MIB, Flags: MachineMemOperand::MOLoad, useAM3);
1028
1029 // If we had an unaligned load of a float we've converted it to an regular
1030 // load. Now we must move from the GRP to the FP register.
1031 if (needVMOV) {
1032 Register MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1033 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1034 TII.get(ARM::VMOVSR), MoveReg)
1035 .addReg(ResultReg));
1036 ResultReg = MoveReg;
1037 }
1038 return true;
1039}
1040
1041bool ARMFastISel::SelectLoad(const Instruction *I) {
1042 // Atomic loads need special handling.
1043 if (cast<LoadInst>(Val: I)->isAtomic())
1044 return false;
1045
1046 const Value *SV = I->getOperand(i: 0);
1047 if (TLI.supportSwiftError()) {
1048 // Swifterror values can come from either a function parameter with
1049 // swifterror attribute or an alloca with swifterror attribute.
1050 if (const Argument *Arg = dyn_cast<Argument>(Val: SV)) {
1051 if (Arg->hasSwiftErrorAttr())
1052 return false;
1053 }
1054
1055 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(Val: SV)) {
1056 if (Alloca->isSwiftError())
1057 return false;
1058 }
1059 }
1060
1061 // Verify we have a legal type before going any further.
1062 MVT VT;
1063 if (!isLoadTypeLegal(Ty: I->getType(), VT))
1064 return false;
1065
1066 // See if we can handle this address.
1067 Address Addr;
1068 if (!ARMComputeAddress(Obj: I->getOperand(i: 0), Addr)) return false;
1069
1070 Register ResultReg;
1071 if (!ARMEmitLoad(VT, ResultReg, Addr, Alignment: cast<LoadInst>(Val: I)->getAlign()))
1072 return false;
1073 updateValueMap(I, Reg: ResultReg);
1074 return true;
1075}
1076
1077bool ARMFastISel::ARMEmitStore(MVT VT, Register SrcReg, Address &Addr,
1078 MaybeAlign Alignment) {
1079 unsigned StrOpc;
1080 bool useAM3 = false;
1081 switch (VT.SimpleTy) {
1082 // This is mostly going to be Neon/vector support.
1083 default: return false;
1084 case MVT::i1: {
1085 Register Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass
1086 : &ARM::GPRRegClass);
1087 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1088 SrcReg = constrainOperandRegClass(II: TII.get(Opcode: Opc), Op: SrcReg, OpNum: 1);
1089 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1090 MCID: TII.get(Opcode: Opc), DestReg: Res)
1091 .addReg(RegNo: SrcReg).addImm(Val: 1));
1092 SrcReg = Res;
1093 [[fallthrough]];
1094 }
1095 case MVT::i8:
1096 if (isThumb2) {
1097 if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
1098 Subtarget->hasV6T2Ops())
1099 StrOpc = ARM::t2STRBi8;
1100 else
1101 StrOpc = ARM::t2STRBi12;
1102 } else {
1103 StrOpc = ARM::STRBi12;
1104 }
1105 break;
1106 case MVT::i16:
1107 if (Alignment && *Alignment < Align(2) &&
1108 !Subtarget->allowsUnalignedMem())
1109 return false;
1110
1111 if (isThumb2) {
1112 if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
1113 Subtarget->hasV6T2Ops())
1114 StrOpc = ARM::t2STRHi8;
1115 else
1116 StrOpc = ARM::t2STRHi12;
1117 } else {
1118 StrOpc = ARM::STRH;
1119 useAM3 = true;
1120 }
1121 break;
1122 case MVT::i32:
1123 if (Alignment && *Alignment < Align(4) &&
1124 !Subtarget->allowsUnalignedMem())
1125 return false;
1126
1127 if (isThumb2) {
1128 if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
1129 Subtarget->hasV6T2Ops())
1130 StrOpc = ARM::t2STRi8;
1131 else
1132 StrOpc = ARM::t2STRi12;
1133 } else {
1134 StrOpc = ARM::STRi12;
1135 }
1136 break;
1137 case MVT::f32:
1138 if (!Subtarget->hasVFP2Base()) return false;
1139 // Unaligned stores need special handling. Floats require word-alignment.
1140 if (Alignment && *Alignment < Align(4)) {
1141 Register MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1142 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1143 TII.get(ARM::VMOVRS), MoveReg)
1144 .addReg(SrcReg));
1145 SrcReg = MoveReg;
1146 VT = MVT::i32;
1147 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1148 } else {
1149 StrOpc = ARM::VSTRS;
1150 }
1151 break;
1152 case MVT::f64:
1153 // Can load and store double precision even without FeatureFP64
1154 if (!Subtarget->hasVFP2Base()) return false;
1155 // FIXME: Unaligned stores need special handling. Doublewords require
1156 // word-alignment.
1157 if (Alignment && *Alignment < Align(4))
1158 return false;
1159
1160 StrOpc = ARM::VSTRD;
1161 break;
1162 }
1163 // Simplify this down to something we can handle.
1164 ARMSimplifyAddress(Addr, VT, useAM3);
1165
1166 // Create the base instruction, then add the operands.
1167 SrcReg = constrainOperandRegClass(II: TII.get(Opcode: StrOpc), Op: SrcReg, OpNum: 0);
1168 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1169 MCID: TII.get(Opcode: StrOpc))
1170 .addReg(RegNo: SrcReg);
1171 AddLoadStoreOperands(VT, Addr, MIB, Flags: MachineMemOperand::MOStore, useAM3);
1172 return true;
1173}
1174
1175bool ARMFastISel::SelectStore(const Instruction *I) {
1176 Value *Op0 = I->getOperand(i: 0);
1177 Register SrcReg;
1178
1179 // Atomic stores need special handling.
1180 if (cast<StoreInst>(Val: I)->isAtomic())
1181 return false;
1182
1183 const Value *PtrV = I->getOperand(i: 1);
1184 if (TLI.supportSwiftError()) {
1185 // Swifterror values can come from either a function parameter with
1186 // swifterror attribute or an alloca with swifterror attribute.
1187 if (const Argument *Arg = dyn_cast<Argument>(Val: PtrV)) {
1188 if (Arg->hasSwiftErrorAttr())
1189 return false;
1190 }
1191
1192 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(Val: PtrV)) {
1193 if (Alloca->isSwiftError())
1194 return false;
1195 }
1196 }
1197
1198 // Verify we have a legal type before going any further.
1199 MVT VT;
1200 if (!isLoadTypeLegal(Ty: I->getOperand(i: 0)->getType(), VT))
1201 return false;
1202
1203 // Get the value to be stored into a register.
1204 SrcReg = getRegForValue(V: Op0);
1205 if (!SrcReg)
1206 return false;
1207
1208 // See if we can handle this address.
1209 Address Addr;
1210 if (!ARMComputeAddress(Obj: I->getOperand(i: 1), Addr))
1211 return false;
1212
1213 if (!ARMEmitStore(VT, SrcReg, Addr, Alignment: cast<StoreInst>(Val: I)->getAlign()))
1214 return false;
1215 return true;
1216}
1217
1218static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1219 switch (Pred) {
1220 // Needs two compares...
1221 case CmpInst::FCMP_ONE:
1222 case CmpInst::FCMP_UEQ:
1223 default:
1224 // AL is our "false" for now. The other two need more compares.
1225 return ARMCC::AL;
1226 case CmpInst::ICMP_EQ:
1227 case CmpInst::FCMP_OEQ:
1228 return ARMCC::EQ;
1229 case CmpInst::ICMP_SGT:
1230 case CmpInst::FCMP_OGT:
1231 return ARMCC::GT;
1232 case CmpInst::ICMP_SGE:
1233 case CmpInst::FCMP_OGE:
1234 return ARMCC::GE;
1235 case CmpInst::ICMP_UGT:
1236 case CmpInst::FCMP_UGT:
1237 return ARMCC::HI;
1238 case CmpInst::FCMP_OLT:
1239 return ARMCC::MI;
1240 case CmpInst::ICMP_ULE:
1241 case CmpInst::FCMP_OLE:
1242 return ARMCC::LS;
1243 case CmpInst::FCMP_ORD:
1244 return ARMCC::VC;
1245 case CmpInst::FCMP_UNO:
1246 return ARMCC::VS;
1247 case CmpInst::FCMP_UGE:
1248 return ARMCC::PL;
1249 case CmpInst::ICMP_SLT:
1250 case CmpInst::FCMP_ULT:
1251 return ARMCC::LT;
1252 case CmpInst::ICMP_SLE:
1253 case CmpInst::FCMP_ULE:
1254 return ARMCC::LE;
1255 case CmpInst::FCMP_UNE:
1256 case CmpInst::ICMP_NE:
1257 return ARMCC::NE;
1258 case CmpInst::ICMP_UGE:
1259 return ARMCC::HS;
1260 case CmpInst::ICMP_ULT:
1261 return ARMCC::LO;
1262 }
1263}
1264
1265bool ARMFastISel::SelectBranch(const Instruction *I) {
1266 const BranchInst *BI = cast<BranchInst>(Val: I);
1267 MachineBasicBlock *TBB = FuncInfo.getMBB(BB: BI->getSuccessor(i: 0));
1268 MachineBasicBlock *FBB = FuncInfo.getMBB(BB: BI->getSuccessor(i: 1));
1269
1270 // Simple branch support.
1271
1272 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1273 // behavior.
1274 if (const CmpInst *CI = dyn_cast<CmpInst>(Val: BI->getCondition())) {
1275 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1276 // Get the compare predicate.
1277 // Try to take advantage of fallthrough opportunities.
1278 CmpInst::Predicate Predicate = CI->getPredicate();
1279 if (FuncInfo.MBB->isLayoutSuccessor(MBB: TBB)) {
1280 std::swap(a&: TBB, b&: FBB);
1281 Predicate = CmpInst::getInversePredicate(pred: Predicate);
1282 }
1283
1284 ARMCC::CondCodes ARMPred = getComparePred(Pred: Predicate);
1285
1286 // We may not handle every CC for now.
1287 if (ARMPred == ARMCC::AL) return false;
1288
1289 // Emit the compare.
1290 if (!ARMEmitCmp(Src1Value: CI->getOperand(i_nocapture: 0), Src2Value: CI->getOperand(i_nocapture: 1), isZExt: CI->isUnsigned()))
1291 return false;
1292
1293 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1294 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(BrOpc))
1295 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1296 finishCondBranch(BranchBB: BI->getParent(), TrueMBB: TBB, FalseMBB: FBB);
1297 return true;
1298 }
1299 } else if (TruncInst *TI = dyn_cast<TruncInst>(Val: BI->getCondition())) {
1300 MVT SourceVT;
1301 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1302 (isLoadTypeLegal(Ty: TI->getOperand(i_nocapture: 0)->getType(), VT&: SourceVT))) {
1303 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1304 Register OpReg = getRegForValue(V: TI->getOperand(i_nocapture: 0));
1305 OpReg = constrainOperandRegClass(II: TII.get(Opcode: TstOpc), Op: OpReg, OpNum: 0);
1306 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1307 MCID: TII.get(Opcode: TstOpc))
1308 .addReg(RegNo: OpReg).addImm(Val: 1));
1309
1310 unsigned CCMode = ARMCC::NE;
1311 if (FuncInfo.MBB->isLayoutSuccessor(MBB: TBB)) {
1312 std::swap(a&: TBB, b&: FBB);
1313 CCMode = ARMCC::EQ;
1314 }
1315
1316 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1317 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(BrOpc))
1318 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1319
1320 finishCondBranch(BranchBB: BI->getParent(), TrueMBB: TBB, FalseMBB: FBB);
1321 return true;
1322 }
1323 } else if (const ConstantInt *CI =
1324 dyn_cast<ConstantInt>(Val: BI->getCondition())) {
1325 uint64_t Imm = CI->getZExtValue();
1326 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1327 fastEmitBranch(MSucc: Target, DbgLoc: MIMD.getDL());
1328 return true;
1329 }
1330
1331 Register CmpReg = getRegForValue(V: BI->getCondition());
1332 if (!CmpReg)
1333 return false;
1334
1335 // We've been divorced from our compare! Our block was split, and
1336 // now our compare lives in a predecessor block. We musn't
1337 // re-compare here, as the children of the compare aren't guaranteed
1338 // live across the block boundary (we *could* check for this).
1339 // Regardless, the compare has been done in the predecessor block,
1340 // and it left a value for us in a virtual register. Ergo, we test
1341 // the one-bit value left in the virtual register.
1342 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1343 CmpReg = constrainOperandRegClass(II: TII.get(Opcode: TstOpc), Op: CmpReg, OpNum: 0);
1344 AddOptionalDefs(
1345 MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: TstOpc))
1346 .addReg(RegNo: CmpReg)
1347 .addImm(Val: 1));
1348
1349 unsigned CCMode = ARMCC::NE;
1350 if (FuncInfo.MBB->isLayoutSuccessor(MBB: TBB)) {
1351 std::swap(a&: TBB, b&: FBB);
1352 CCMode = ARMCC::EQ;
1353 }
1354
1355 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1356 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(BrOpc))
1357 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1358 finishCondBranch(BranchBB: BI->getParent(), TrueMBB: TBB, FalseMBB: FBB);
1359 return true;
1360}
1361
1362bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1363 Register AddrReg = getRegForValue(V: I->getOperand(i: 0));
1364 if (!AddrReg)
1365 return false;
1366
1367 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1368 assert(isThumb2 || Subtarget->hasV4TOps());
1369
1370 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1371 MCID: TII.get(Opcode: Opc)).addReg(RegNo: AddrReg));
1372
1373 const IndirectBrInst *IB = cast<IndirectBrInst>(Val: I);
1374 for (const BasicBlock *SuccBB : IB->successors())
1375 FuncInfo.MBB->addSuccessor(Succ: FuncInfo.getMBB(BB: SuccBB));
1376
1377 return true;
1378}
1379
1380bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1381 bool isZExt) {
1382 Type *Ty = Src1Value->getType();
1383 EVT SrcEVT = TLI.getValueType(DL, Ty, AllowUnknown: true);
1384 if (!SrcEVT.isSimple()) return false;
1385 MVT SrcVT = SrcEVT.getSimpleVT();
1386
1387 if (Ty->isFloatTy() && !Subtarget->hasVFP2Base())
1388 return false;
1389
1390 if (Ty->isDoubleTy() && (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()))
1391 return false;
1392
1393 // Check to see if the 2nd operand is a constant that we can encode directly
1394 // in the compare.
1395 int Imm = 0;
1396 bool UseImm = false;
1397 bool isNegativeImm = false;
1398 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1399 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1400 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Val: Src2Value)) {
1401 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1402 SrcVT == MVT::i1) {
1403 const APInt &CIVal = ConstInt->getValue();
1404 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1405 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1406 // then a cmn, because there is no way to represent 2147483648 as a
1407 // signed 32-bit int.
1408 if (Imm < 0 && Imm != (int)0x80000000) {
1409 isNegativeImm = true;
1410 Imm = -Imm;
1411 }
1412 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Arg: Imm) != -1) :
1413 (ARM_AM::getSOImmVal(Arg: Imm) != -1);
1414 }
1415 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Val: Src2Value)) {
1416 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1417 if (ConstFP->isZero() && !ConstFP->isNegative())
1418 UseImm = true;
1419 }
1420
1421 unsigned CmpOpc;
1422 bool isICmp = true;
1423 bool needsExt = false;
1424 switch (SrcVT.SimpleTy) {
1425 default: return false;
1426 // TODO: Verify compares.
1427 case MVT::f32:
1428 isICmp = false;
1429 CmpOpc = UseImm ? ARM::VCMPZS : ARM::VCMPS;
1430 break;
1431 case MVT::f64:
1432 isICmp = false;
1433 CmpOpc = UseImm ? ARM::VCMPZD : ARM::VCMPD;
1434 break;
1435 case MVT::i1:
1436 case MVT::i8:
1437 case MVT::i16:
1438 needsExt = true;
1439 [[fallthrough]];
1440 case MVT::i32:
1441 if (isThumb2) {
1442 if (!UseImm)
1443 CmpOpc = ARM::t2CMPrr;
1444 else
1445 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1446 } else {
1447 if (!UseImm)
1448 CmpOpc = ARM::CMPrr;
1449 else
1450 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1451 }
1452 break;
1453 }
1454
1455 Register SrcReg1 = getRegForValue(V: Src1Value);
1456 if (!SrcReg1)
1457 return false;
1458
1459 Register SrcReg2;
1460 if (!UseImm) {
1461 SrcReg2 = getRegForValue(V: Src2Value);
1462 if (!SrcReg2)
1463 return false;
1464 }
1465
1466 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1467 if (needsExt) {
1468 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1469 if (!SrcReg1)
1470 return false;
1471 if (!UseImm) {
1472 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1473 if (!SrcReg2)
1474 return false;
1475 }
1476 }
1477
1478 const MCInstrDesc &II = TII.get(Opcode: CmpOpc);
1479 SrcReg1 = constrainOperandRegClass(II, Op: SrcReg1, OpNum: 0);
1480 if (!UseImm) {
1481 SrcReg2 = constrainOperandRegClass(II, Op: SrcReg2, OpNum: 1);
1482 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II)
1483 .addReg(RegNo: SrcReg1).addReg(RegNo: SrcReg2));
1484 } else {
1485 MachineInstrBuilder MIB;
1486 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II)
1487 .addReg(RegNo: SrcReg1);
1488
1489 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1490 if (isICmp)
1491 MIB.addImm(Val: Imm);
1492 AddOptionalDefs(MIB);
1493 }
1494
1495 // For floating point we need to move the result to a comparison register
1496 // that we can then use for branches.
1497 if (Ty->isFloatTy() || Ty->isDoubleTy())
1498 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1499 TII.get(ARM::FMSTAT)));
1500 return true;
1501}
1502
1503bool ARMFastISel::SelectCmp(const Instruction *I) {
1504 const CmpInst *CI = cast<CmpInst>(Val: I);
1505
1506 // Get the compare predicate.
1507 ARMCC::CondCodes ARMPred = getComparePred(Pred: CI->getPredicate());
1508
1509 // We may not handle every CC for now.
1510 if (ARMPred == ARMCC::AL) return false;
1511
1512 // Emit the compare.
1513 if (!ARMEmitCmp(Src1Value: CI->getOperand(i_nocapture: 0), Src2Value: CI->getOperand(i_nocapture: 1), isZExt: CI->isUnsigned()))
1514 return false;
1515
1516 // Now set a register based on the comparison. Explicitly set the predicates
1517 // here.
1518 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1519 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
1520 : &ARM::GPRRegClass;
1521 Register DestReg = createResultReg(RC);
1522 Constant *Zero = ConstantInt::get(Ty: Type::getInt32Ty(C&: *Context), V: 0);
1523 Register ZeroReg = fastMaterializeConstant(C: Zero);
1524 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1525 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(MovCCOpc), DestReg)
1526 .addReg(ZeroReg).addImm(1)
1527 .addImm(ARMPred).addReg(ARM::CPSR);
1528
1529 updateValueMap(I, Reg: DestReg);
1530 return true;
1531}
1532
1533bool ARMFastISel::SelectFPExt(const Instruction *I) {
1534 // Make sure we have VFP and that we're extending float to double.
1535 if (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()) return false;
1536
1537 Value *V = I->getOperand(i: 0);
1538 if (!I->getType()->isDoubleTy() ||
1539 !V->getType()->isFloatTy()) return false;
1540
1541 Register Op = getRegForValue(V);
1542 if (!Op)
1543 return false;
1544
1545 Register Result = createResultReg(&ARM::DPRRegClass);
1546 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1547 TII.get(ARM::VCVTDS), Result)
1548 .addReg(Op));
1549 updateValueMap(I, Reg: Result);
1550 return true;
1551}
1552
1553bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1554 // Make sure we have VFP and that we're truncating double to float.
1555 if (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()) return false;
1556
1557 Value *V = I->getOperand(i: 0);
1558 if (!(I->getType()->isFloatTy() &&
1559 V->getType()->isDoubleTy())) return false;
1560
1561 Register Op = getRegForValue(V);
1562 if (!Op)
1563 return false;
1564
1565 Register Result = createResultReg(&ARM::SPRRegClass);
1566 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1567 TII.get(ARM::VCVTSD), Result)
1568 .addReg(Op));
1569 updateValueMap(I, Reg: Result);
1570 return true;
1571}
1572
1573bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1574 // Make sure we have VFP.
1575 if (!Subtarget->hasVFP2Base()) return false;
1576
1577 MVT DstVT;
1578 Type *Ty = I->getType();
1579 if (!isTypeLegal(Ty, VT&: DstVT))
1580 return false;
1581
1582 Value *Src = I->getOperand(i: 0);
1583 EVT SrcEVT = TLI.getValueType(DL, Ty: Src->getType(), AllowUnknown: true);
1584 if (!SrcEVT.isSimple())
1585 return false;
1586 MVT SrcVT = SrcEVT.getSimpleVT();
1587 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1588 return false;
1589
1590 Register SrcReg = getRegForValue(V: Src);
1591 if (!SrcReg)
1592 return false;
1593
1594 // Handle sign-extension.
1595 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1596 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1597 /*isZExt*/!isSigned);
1598 if (!SrcReg)
1599 return false;
1600 }
1601
1602 // The conversion routine works on fp-reg to fp-reg and the operand above
1603 // was an integer, move it to the fp registers if possible.
1604 Register FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1605 if (!FP)
1606 return false;
1607
1608 unsigned Opc;
1609 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1610 else if (Ty->isDoubleTy() && Subtarget->hasFP64())
1611 Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1612 else return false;
1613
1614 Register ResultReg = createResultReg(RC: TLI.getRegClassFor(VT: DstVT));
1615 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1616 MCID: TII.get(Opcode: Opc), DestReg: ResultReg).addReg(RegNo: FP));
1617 updateValueMap(I, Reg: ResultReg);
1618 return true;
1619}
1620
1621bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1622 // Make sure we have VFP.
1623 if (!Subtarget->hasVFP2Base()) return false;
1624
1625 MVT DstVT;
1626 Type *RetTy = I->getType();
1627 if (!isTypeLegal(Ty: RetTy, VT&: DstVT))
1628 return false;
1629
1630 Register Op = getRegForValue(V: I->getOperand(i: 0));
1631 if (!Op)
1632 return false;
1633
1634 unsigned Opc;
1635 Type *OpTy = I->getOperand(i: 0)->getType();
1636 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1637 else if (OpTy->isDoubleTy() && Subtarget->hasFP64())
1638 Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1639 else return false;
1640
1641 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1642 Register ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1643 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1644 MCID: TII.get(Opcode: Opc), DestReg: ResultReg).addReg(RegNo: Op));
1645
1646 // This result needs to be in an integer register, but the conversion only
1647 // takes place in fp-regs.
1648 Register IntReg = ARMMoveToIntReg(VT: DstVT, SrcReg: ResultReg);
1649 if (!IntReg)
1650 return false;
1651
1652 updateValueMap(I, Reg: IntReg);
1653 return true;
1654}
1655
1656bool ARMFastISel::SelectSelect(const Instruction *I) {
1657 MVT VT;
1658 if (!isTypeLegal(Ty: I->getType(), VT))
1659 return false;
1660
1661 // Things need to be register sized for register moves.
1662 if (VT != MVT::i32) return false;
1663
1664 Register CondReg = getRegForValue(V: I->getOperand(i: 0));
1665 if (!CondReg)
1666 return false;
1667 Register Op1Reg = getRegForValue(V: I->getOperand(i: 1));
1668 if (!Op1Reg)
1669 return false;
1670
1671 // Check to see if we can use an immediate in the conditional move.
1672 int Imm = 0;
1673 bool UseImm = false;
1674 bool isNegativeImm = false;
1675 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Val: I->getOperand(i: 2))) {
1676 assert(VT == MVT::i32 && "Expecting an i32.");
1677 Imm = (int)ConstInt->getValue().getZExtValue();
1678 if (Imm < 0) {
1679 isNegativeImm = true;
1680 Imm = ~Imm;
1681 }
1682 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Arg: Imm) != -1) :
1683 (ARM_AM::getSOImmVal(Arg: Imm) != -1);
1684 }
1685
1686 Register Op2Reg;
1687 if (!UseImm) {
1688 Op2Reg = getRegForValue(V: I->getOperand(i: 2));
1689 if (!Op2Reg)
1690 return false;
1691 }
1692
1693 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1694 CondReg = constrainOperandRegClass(II: TII.get(Opcode: TstOpc), Op: CondReg, OpNum: 0);
1695 AddOptionalDefs(
1696 MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: TstOpc))
1697 .addReg(RegNo: CondReg)
1698 .addImm(Val: 1));
1699
1700 unsigned MovCCOpc;
1701 const TargetRegisterClass *RC;
1702 if (!UseImm) {
1703 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1704 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1705 } else {
1706 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1707 if (!isNegativeImm)
1708 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1709 else
1710 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1711 }
1712 Register ResultReg = createResultReg(RC);
1713 if (!UseImm) {
1714 Op2Reg = constrainOperandRegClass(II: TII.get(Opcode: MovCCOpc), Op: Op2Reg, OpNum: 1);
1715 Op1Reg = constrainOperandRegClass(II: TII.get(Opcode: MovCCOpc), Op: Op1Reg, OpNum: 2);
1716 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(MovCCOpc),
1717 ResultReg)
1718 .addReg(Op2Reg)
1719 .addReg(Op1Reg)
1720 .addImm(ARMCC::NE)
1721 .addReg(ARM::CPSR);
1722 } else {
1723 Op1Reg = constrainOperandRegClass(II: TII.get(Opcode: MovCCOpc), Op: Op1Reg, OpNum: 1);
1724 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(MovCCOpc),
1725 ResultReg)
1726 .addReg(Op1Reg)
1727 .addImm(Imm)
1728 .addImm(ARMCC::EQ)
1729 .addReg(ARM::CPSR);
1730 }
1731 updateValueMap(I, Reg: ResultReg);
1732 return true;
1733}
1734
1735bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1736 MVT VT;
1737 Type *Ty = I->getType();
1738 if (!isTypeLegal(Ty, VT))
1739 return false;
1740
1741 // If we have integer div support we should have selected this automagically.
1742 // In case we have a real miss go ahead and return false and we'll pick
1743 // it up later.
1744 if (Subtarget->hasDivideInThumbMode())
1745 return false;
1746
1747 // Otherwise emit a libcall.
1748 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1749 if (VT == MVT::i8)
1750 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1751 else if (VT == MVT::i16)
1752 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1753 else if (VT == MVT::i32)
1754 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1755 else if (VT == MVT::i64)
1756 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1757 else if (VT == MVT::i128)
1758 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1759 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1760
1761 return ARMEmitLibcall(I, Call: LC);
1762}
1763
1764bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1765 MVT VT;
1766 Type *Ty = I->getType();
1767 if (!isTypeLegal(Ty, VT))
1768 return false;
1769
1770 // Many ABIs do not provide a libcall for standalone remainder, so we need to
1771 // use divrem (see the RTABI 4.3.1). Since FastISel can't handle non-double
1772 // multi-reg returns, we'll have to bail out.
1773 if (!TLI.hasStandaloneRem(VT)) {
1774 return false;
1775 }
1776
1777 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1778 if (VT == MVT::i8)
1779 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1780 else if (VT == MVT::i16)
1781 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1782 else if (VT == MVT::i32)
1783 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1784 else if (VT == MVT::i64)
1785 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1786 else if (VT == MVT::i128)
1787 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1788 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1789
1790 return ARMEmitLibcall(I, Call: LC);
1791}
1792
1793bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1794 EVT DestVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
1795
1796 // We can get here in the case when we have a binary operation on a non-legal
1797 // type and the target independent selector doesn't know how to handle it.
1798 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1799 return false;
1800
1801 unsigned Opc;
1802 switch (ISDOpcode) {
1803 default: return false;
1804 case ISD::ADD:
1805 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1806 break;
1807 case ISD::OR:
1808 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1809 break;
1810 case ISD::SUB:
1811 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1812 break;
1813 }
1814
1815 Register SrcReg1 = getRegForValue(V: I->getOperand(i: 0));
1816 if (!SrcReg1)
1817 return false;
1818
1819 // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1820 // in the instruction, rather then materializing the value in a register.
1821 Register SrcReg2 = getRegForValue(V: I->getOperand(i: 1));
1822 if (!SrcReg2)
1823 return false;
1824
1825 Register ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1826 SrcReg1 = constrainOperandRegClass(II: TII.get(Opcode: Opc), Op: SrcReg1, OpNum: 1);
1827 SrcReg2 = constrainOperandRegClass(II: TII.get(Opcode: Opc), Op: SrcReg2, OpNum: 2);
1828 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1829 MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
1830 .addReg(RegNo: SrcReg1).addReg(RegNo: SrcReg2));
1831 updateValueMap(I, Reg: ResultReg);
1832 return true;
1833}
1834
1835bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1836 EVT FPVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
1837 if (!FPVT.isSimple()) return false;
1838 MVT VT = FPVT.getSimpleVT();
1839
1840 // FIXME: Support vector types where possible.
1841 if (VT.isVector())
1842 return false;
1843
1844 // We can get here in the case when we want to use NEON for our fp
1845 // operations, but can't figure out how to. Just use the vfp instructions
1846 // if we have them.
1847 // FIXME: It'd be nice to use NEON instructions.
1848 Type *Ty = I->getType();
1849 if (Ty->isFloatTy() && !Subtarget->hasVFP2Base())
1850 return false;
1851 if (Ty->isDoubleTy() && (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()))
1852 return false;
1853
1854 unsigned Opc;
1855 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1856 switch (ISDOpcode) {
1857 default: return false;
1858 case ISD::FADD:
1859 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1860 break;
1861 case ISD::FSUB:
1862 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1863 break;
1864 case ISD::FMUL:
1865 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1866 break;
1867 }
1868 Register Op1 = getRegForValue(V: I->getOperand(i: 0));
1869 if (!Op1)
1870 return false;
1871
1872 Register Op2 = getRegForValue(V: I->getOperand(i: 1));
1873 if (!Op2)
1874 return false;
1875
1876 Register ResultReg = createResultReg(RC: TLI.getRegClassFor(VT: VT.SimpleTy));
1877 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1878 MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
1879 .addReg(RegNo: Op1).addReg(RegNo: Op2));
1880 updateValueMap(I, Reg: ResultReg);
1881 return true;
1882}
1883
1884// Call Handling Code
1885
1886// This is largely taken directly from CCAssignFnForNode
1887// TODO: We may not support all of this.
1888CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1889 bool Return,
1890 bool isVarArg) {
1891 switch (CC) {
1892 default:
1893 report_fatal_error(reason: "Unsupported calling convention");
1894 case CallingConv::Fast:
1895 if (Subtarget->hasVFP2Base() && !isVarArg) {
1896 if (!Subtarget->isAAPCS_ABI())
1897 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1898 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1899 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1900 }
1901 [[fallthrough]];
1902 case CallingConv::C:
1903 case CallingConv::CXX_FAST_TLS:
1904 // Use target triple & subtarget features to do actual dispatch.
1905 if (Subtarget->isAAPCS_ABI()) {
1906 if (Subtarget->hasFPRegs() &&
1907 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1908 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1909 else
1910 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1911 } else {
1912 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1913 }
1914 case CallingConv::ARM_AAPCS_VFP:
1915 case CallingConv::Swift:
1916 case CallingConv::SwiftTail:
1917 if (!isVarArg)
1918 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1919 // Fall through to soft float variant, variadic functions don't
1920 // use hard floating point ABI.
1921 [[fallthrough]];
1922 case CallingConv::ARM_AAPCS:
1923 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1924 case CallingConv::ARM_APCS:
1925 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1926 case CallingConv::GHC:
1927 if (Return)
1928 report_fatal_error(reason: "Can't return in GHC call convention");
1929 else
1930 return CC_ARM_APCS_GHC;
1931 case CallingConv::CFGuard_Check:
1932 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
1933 }
1934}
1935
1936bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1937 SmallVectorImpl<Register> &ArgRegs,
1938 SmallVectorImpl<MVT> &ArgVTs,
1939 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1940 SmallVectorImpl<Register> &RegArgs,
1941 CallingConv::ID CC,
1942 unsigned &NumBytes,
1943 bool isVarArg) {
1944 SmallVector<CCValAssign, 16> ArgLocs;
1945 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context);
1946 CCInfo.AnalyzeCallOperands(ArgVTs, Flags&: ArgFlags,
1947 Fn: CCAssignFnForCall(CC, Return: false, isVarArg));
1948
1949 // Check that we can handle all of the arguments. If we can't, then bail out
1950 // now before we add code to the MBB.
1951 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1952 CCValAssign &VA = ArgLocs[i];
1953 MVT ArgVT = ArgVTs[VA.getValNo()];
1954
1955 // We don't handle NEON/vector parameters yet.
1956 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1957 return false;
1958
1959 // Now copy/store arg to correct locations.
1960 if (VA.isRegLoc() && !VA.needsCustom()) {
1961 continue;
1962 } else if (VA.needsCustom()) {
1963 // TODO: We need custom lowering for vector (v2f64) args.
1964 if (VA.getLocVT() != MVT::f64 ||
1965 // TODO: Only handle register args for now.
1966 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1967 return false;
1968 } else {
1969 switch (ArgVT.SimpleTy) {
1970 default:
1971 return false;
1972 case MVT::i1:
1973 case MVT::i8:
1974 case MVT::i16:
1975 case MVT::i32:
1976 break;
1977 case MVT::f32:
1978 if (!Subtarget->hasVFP2Base())
1979 return false;
1980 break;
1981 case MVT::f64:
1982 if (!Subtarget->hasVFP2Base())
1983 return false;
1984 break;
1985 }
1986 }
1987 }
1988
1989 // At the point, we are able to handle the call's arguments in fast isel.
1990
1991 // Get a count of how many bytes are to be pushed on the stack.
1992 NumBytes = CCInfo.getStackSize();
1993
1994 // Issue CALLSEQ_START
1995 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1996 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1997 MCID: TII.get(Opcode: AdjStackDown))
1998 .addImm(Val: NumBytes).addImm(Val: 0));
1999
2000 // Process the args.
2001 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2002 CCValAssign &VA = ArgLocs[i];
2003 const Value *ArgVal = Args[VA.getValNo()];
2004 Register Arg = ArgRegs[VA.getValNo()];
2005 MVT ArgVT = ArgVTs[VA.getValNo()];
2006
2007 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
2008 "We don't handle NEON/vector parameters yet.");
2009
2010 // Handle arg promotion, etc.
2011 switch (VA.getLocInfo()) {
2012 case CCValAssign::Full: break;
2013 case CCValAssign::SExt: {
2014 MVT DestVT = VA.getLocVT();
2015 Arg = ARMEmitIntExt(SrcVT: ArgVT, SrcReg: Arg, DestVT, /*isZExt*/false);
2016 assert(Arg && "Failed to emit a sext");
2017 ArgVT = DestVT;
2018 break;
2019 }
2020 case CCValAssign::AExt:
2021 // Intentional fall-through. Handle AExt and ZExt.
2022 case CCValAssign::ZExt: {
2023 MVT DestVT = VA.getLocVT();
2024 Arg = ARMEmitIntExt(SrcVT: ArgVT, SrcReg: Arg, DestVT, /*isZExt*/true);
2025 assert(Arg && "Failed to emit a zext");
2026 ArgVT = DestVT;
2027 break;
2028 }
2029 case CCValAssign::BCvt: {
2030 Register BC = fastEmit_r(VT: ArgVT, RetVT: VA.getLocVT(), Opcode: ISD::BITCAST, Op0: Arg);
2031 assert(BC && "Failed to emit a bitcast!");
2032 Arg = BC;
2033 ArgVT = VA.getLocVT();
2034 break;
2035 }
2036 default: llvm_unreachable("Unknown arg promotion!");
2037 }
2038
2039 // Now copy/store arg to correct locations.
2040 if (VA.isRegLoc() && !VA.needsCustom()) {
2041 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2042 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: VA.getLocReg()).addReg(RegNo: Arg);
2043 RegArgs.push_back(Elt: VA.getLocReg());
2044 } else if (VA.needsCustom()) {
2045 // TODO: We need custom lowering for vector (v2f64) args.
2046 assert(VA.getLocVT() == MVT::f64 &&
2047 "Custom lowering for v2f64 args not available");
2048
2049 // FIXME: ArgLocs[++i] may extend beyond ArgLocs.size()
2050 CCValAssign &NextVA = ArgLocs[++i];
2051
2052 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2053 "We only handle register args!");
2054
2055 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2056 TII.get(ARM::VMOVRRD), VA.getLocReg())
2057 .addReg(NextVA.getLocReg(), RegState::Define)
2058 .addReg(Arg));
2059 RegArgs.push_back(Elt: VA.getLocReg());
2060 RegArgs.push_back(Elt: NextVA.getLocReg());
2061 } else {
2062 assert(VA.isMemLoc());
2063 // Need to store on the stack.
2064
2065 // Don't emit stores for undef values.
2066 if (isa<UndefValue>(Val: ArgVal))
2067 continue;
2068
2069 Address Addr;
2070 Addr.setKind(Address::RegBase);
2071 Addr.setReg(ARM::SP);
2072 Addr.setOffset(VA.getLocMemOffset());
2073
2074 bool EmitRet = ARMEmitStore(VT: ArgVT, SrcReg: Arg, Addr); (void)EmitRet;
2075 assert(EmitRet && "Could not emit a store for argument!");
2076 }
2077 }
2078
2079 return true;
2080}
2081
2082bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
2083 const Instruction *I, CallingConv::ID CC,
2084 unsigned &NumBytes, bool isVarArg) {
2085 // Issue CALLSEQ_END
2086 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2087 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2088 MCID: TII.get(Opcode: AdjStackUp))
2089 .addImm(Val: NumBytes).addImm(Val: -1ULL));
2090
2091 // Now the return value.
2092 if (RetVT != MVT::isVoid) {
2093 SmallVector<CCValAssign, 16> RVLocs;
2094 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2095 CCInfo.AnalyzeCallResult(VT: RetVT, Fn: CCAssignFnForCall(CC, Return: true, isVarArg));
2096
2097 // Copy all of the result registers out of their specified physreg.
2098 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2099 // For this move we copy into two registers and then move into the
2100 // double fp reg we want.
2101 MVT DestVT = RVLocs[0].getValVT();
2102 const TargetRegisterClass* DstRC = TLI.getRegClassFor(VT: DestVT);
2103 Register ResultReg = createResultReg(RC: DstRC);
2104 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2105 TII.get(ARM::VMOVDRR), ResultReg)
2106 .addReg(RVLocs[0].getLocReg())
2107 .addReg(RVLocs[1].getLocReg()));
2108
2109 UsedRegs.push_back(Elt: RVLocs[0].getLocReg());
2110 UsedRegs.push_back(Elt: RVLocs[1].getLocReg());
2111
2112 // Finally update the result.
2113 updateValueMap(I, Reg: ResultReg);
2114 } else {
2115 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2116 MVT CopyVT = RVLocs[0].getValVT();
2117
2118 // Special handling for extended integers.
2119 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2120 CopyVT = MVT::i32;
2121
2122 const TargetRegisterClass* DstRC = TLI.getRegClassFor(VT: CopyVT);
2123
2124 Register ResultReg = createResultReg(RC: DstRC);
2125 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2126 MCID: TII.get(Opcode: TargetOpcode::COPY),
2127 DestReg: ResultReg).addReg(RegNo: RVLocs[0].getLocReg());
2128 UsedRegs.push_back(Elt: RVLocs[0].getLocReg());
2129
2130 // Finally update the result.
2131 updateValueMap(I, Reg: ResultReg);
2132 }
2133 }
2134
2135 return true;
2136}
2137
2138bool ARMFastISel::SelectRet(const Instruction *I) {
2139 const ReturnInst *Ret = cast<ReturnInst>(Val: I);
2140 const Function &F = *I->getParent()->getParent();
2141 const bool IsCmseNSEntry = F.hasFnAttribute(Kind: "cmse_nonsecure_entry");
2142
2143 if (!FuncInfo.CanLowerReturn)
2144 return false;
2145
2146 if (TLI.supportSwiftError() &&
2147 F.getAttributes().hasAttrSomewhere(Attribute::SwiftError))
2148 return false;
2149
2150 if (TLI.supportSplitCSR(MF: FuncInfo.MF))
2151 return false;
2152
2153 // Build a list of return value registers.
2154 SmallVector<Register, 4> RetRegs;
2155
2156 CallingConv::ID CC = F.getCallingConv();
2157 if (Ret->getNumOperands() > 0) {
2158 SmallVector<ISD::OutputArg, 4> Outs;
2159 GetReturnInfo(CC, ReturnType: F.getReturnType(), attr: F.getAttributes(), Outs, TLI, DL);
2160
2161 // Analyze operands of the call, assigning locations to each operand.
2162 SmallVector<CCValAssign, 16> ValLocs;
2163 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
2164 CCInfo.AnalyzeReturn(Outs, Fn: CCAssignFnForCall(CC, Return: true /* is Ret */,
2165 isVarArg: F.isVarArg()));
2166
2167 const Value *RV = Ret->getOperand(i_nocapture: 0);
2168 Register Reg = getRegForValue(V: RV);
2169 if (!Reg)
2170 return false;
2171
2172 // Only handle a single return value for now.
2173 if (ValLocs.size() != 1)
2174 return false;
2175
2176 CCValAssign &VA = ValLocs[0];
2177
2178 // Don't bother handling odd stuff for now.
2179 if (VA.getLocInfo() != CCValAssign::Full)
2180 return false;
2181 // Only handle register returns for now.
2182 if (!VA.isRegLoc())
2183 return false;
2184
2185 Register SrcReg = Reg + VA.getValNo();
2186 EVT RVEVT = TLI.getValueType(DL, Ty: RV->getType());
2187 if (!RVEVT.isSimple()) return false;
2188 MVT RVVT = RVEVT.getSimpleVT();
2189 MVT DestVT = VA.getValVT();
2190 // Special handling for extended integers.
2191 if (RVVT != DestVT) {
2192 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2193 return false;
2194
2195 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2196
2197 // Perform extension if flagged as either zext or sext. Otherwise, do
2198 // nothing.
2199 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2200 SrcReg = ARMEmitIntExt(SrcVT: RVVT, SrcReg, DestVT, isZExt: Outs[0].Flags.isZExt());
2201 if (!SrcReg)
2202 return false;
2203 }
2204 }
2205
2206 // Make the copy.
2207 Register DstReg = VA.getLocReg();
2208 const TargetRegisterClass* SrcRC = MRI.getRegClass(Reg: SrcReg);
2209 // Avoid a cross-class copy. This is very unlikely.
2210 if (!SrcRC->contains(Reg: DstReg))
2211 return false;
2212 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2213 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: DstReg).addReg(RegNo: SrcReg);
2214
2215 // Add register to return instruction.
2216 RetRegs.push_back(Elt: VA.getLocReg());
2217 }
2218
2219 unsigned RetOpc;
2220 if (IsCmseNSEntry)
2221 if (isThumb2)
2222 RetOpc = ARM::tBXNS_RET;
2223 else
2224 llvm_unreachable("CMSE not valid for non-Thumb targets");
2225 else
2226 RetOpc = Subtarget->getReturnOpcode();
2227
2228 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2229 MCID: TII.get(Opcode: RetOpc));
2230 AddOptionalDefs(MIB);
2231 for (Register R : RetRegs)
2232 MIB.addReg(RegNo: R, flags: RegState::Implicit);
2233 return true;
2234}
2235
2236unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2237 if (UseReg)
2238 return isThumb2 ? gettBLXrOpcode(MF: *MF) : getBLXOpcode(MF: *MF);
2239 else
2240 return isThumb2 ? ARM::tBL : ARM::BL;
2241}
2242
2243Register ARMFastISel::getLibcallReg(const Twine &Name) {
2244 // Manually compute the global's type to avoid building it when unnecessary.
2245 Type *GVTy = PointerType::get(C&: *Context, /*AS=*/AddressSpace: 0);
2246 EVT LCREVT = TLI.getValueType(DL, Ty: GVTy);
2247 if (!LCREVT.isSimple())
2248 return Register();
2249
2250 GlobalValue *GV = M.getNamedGlobal(Name: Name.str());
2251 if (!GV)
2252 GV = new GlobalVariable(M, Type::getInt32Ty(C&: *Context), false,
2253 GlobalValue::ExternalLinkage, nullptr, Name);
2254
2255 return ARMMaterializeGV(GV, VT: LCREVT.getSimpleVT());
2256}
2257
2258// A quick function that will emit a call for a named libcall in F with the
2259// vector of passed arguments for the Instruction in I. We can assume that we
2260// can emit a call for any libcall we can produce. This is an abridged version
2261// of the full call infrastructure since we won't need to worry about things
2262// like computed function pointers or strange arguments at call sites.
2263// TODO: Try to unify this and the normal call bits for ARM, then try to unify
2264// with X86.
2265bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2266 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2267
2268 // Handle *simple* calls for now.
2269 Type *RetTy = I->getType();
2270 MVT RetVT;
2271 if (RetTy->isVoidTy())
2272 RetVT = MVT::isVoid;
2273 else if (!isTypeLegal(Ty: RetTy, VT&: RetVT))
2274 return false;
2275
2276 // Can't handle non-double multi-reg retvals.
2277 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2278 SmallVector<CCValAssign, 16> RVLocs;
2279 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2280 CCInfo.AnalyzeCallResult(VT: RetVT, Fn: CCAssignFnForCall(CC, Return: true, isVarArg: false));
2281 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2282 return false;
2283 }
2284
2285 // Set up the argument vectors.
2286 SmallVector<Value*, 8> Args;
2287 SmallVector<Register, 8> ArgRegs;
2288 SmallVector<MVT, 8> ArgVTs;
2289 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2290 Args.reserve(N: I->getNumOperands());
2291 ArgRegs.reserve(N: I->getNumOperands());
2292 ArgVTs.reserve(N: I->getNumOperands());
2293 ArgFlags.reserve(N: I->getNumOperands());
2294 for (Value *Op : I->operands()) {
2295 Register Arg = getRegForValue(V: Op);
2296 if (!Arg)
2297 return false;
2298
2299 Type *ArgTy = Op->getType();
2300 MVT ArgVT;
2301 if (!isTypeLegal(Ty: ArgTy, VT&: ArgVT)) return false;
2302
2303 ISD::ArgFlagsTy Flags;
2304 Flags.setOrigAlign(DL.getABITypeAlign(Ty: ArgTy));
2305
2306 Args.push_back(Elt: Op);
2307 ArgRegs.push_back(Elt: Arg);
2308 ArgVTs.push_back(Elt: ArgVT);
2309 ArgFlags.push_back(Elt: Flags);
2310 }
2311
2312 // Handle the arguments now that we've gotten them.
2313 SmallVector<Register, 4> RegArgs;
2314 unsigned NumBytes;
2315 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2316 RegArgs, CC, NumBytes, isVarArg: false))
2317 return false;
2318
2319 Register CalleeReg;
2320 if (Subtarget->genLongCalls()) {
2321 CalleeReg = getLibcallReg(Name: TLI.getLibcallName(Call));
2322 if (!CalleeReg)
2323 return false;
2324 }
2325
2326 // Issue the call.
2327 unsigned CallOpc = ARMSelectCallOp(UseReg: Subtarget->genLongCalls());
2328 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt,
2329 MIMD, MCID: TII.get(Opcode: CallOpc));
2330 // BL / BLX don't take a predicate, but tBL / tBLX do.
2331 if (isThumb2)
2332 MIB.add(MOs: predOps(Pred: ARMCC::AL));
2333 if (Subtarget->genLongCalls()) {
2334 CalleeReg =
2335 constrainOperandRegClass(II: TII.get(Opcode: CallOpc), Op: CalleeReg, OpNum: isThumb2 ? 2 : 0);
2336 MIB.addReg(RegNo: CalleeReg);
2337 } else
2338 MIB.addExternalSymbol(FnName: TLI.getLibcallName(Call));
2339
2340 // Add implicit physical register uses to the call.
2341 for (Register R : RegArgs)
2342 MIB.addReg(RegNo: R, flags: RegState::Implicit);
2343
2344 // Add a register mask with the call-preserved registers.
2345 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2346 MIB.addRegMask(Mask: TRI.getCallPreservedMask(MF: *FuncInfo.MF, CC));
2347
2348 // Finish off the call including any return values.
2349 SmallVector<Register, 4> UsedRegs;
2350 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg: false)) return false;
2351
2352 // Set all unused physreg defs as dead.
2353 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2354
2355 return true;
2356}
2357
2358bool ARMFastISel::SelectCall(const Instruction *I,
2359 const char *IntrMemName = nullptr) {
2360 const CallInst *CI = cast<CallInst>(Val: I);
2361 const Value *Callee = CI->getCalledOperand();
2362
2363 // Can't handle inline asm.
2364 if (isa<InlineAsm>(Val: Callee)) return false;
2365
2366 // Allow SelectionDAG isel to handle tail calls.
2367 if (CI->isTailCall()) return false;
2368
2369 // Check the calling convention.
2370 CallingConv::ID CC = CI->getCallingConv();
2371
2372 // TODO: Avoid some calling conventions?
2373
2374 FunctionType *FTy = CI->getFunctionType();
2375 bool isVarArg = FTy->isVarArg();
2376
2377 // Handle *simple* calls for now.
2378 Type *RetTy = I->getType();
2379 MVT RetVT;
2380 if (RetTy->isVoidTy())
2381 RetVT = MVT::isVoid;
2382 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2383 RetVT != MVT::i8 && RetVT != MVT::i1)
2384 return false;
2385
2386 // Can't handle non-double multi-reg retvals.
2387 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2388 RetVT != MVT::i16 && RetVT != MVT::i32) {
2389 SmallVector<CCValAssign, 16> RVLocs;
2390 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2391 CCInfo.AnalyzeCallResult(VT: RetVT, Fn: CCAssignFnForCall(CC, Return: true, isVarArg));
2392 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2393 return false;
2394 }
2395
2396 // Set up the argument vectors.
2397 SmallVector<Value*, 8> Args;
2398 SmallVector<Register, 8> ArgRegs;
2399 SmallVector<MVT, 8> ArgVTs;
2400 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2401 unsigned arg_size = CI->arg_size();
2402 Args.reserve(N: arg_size);
2403 ArgRegs.reserve(N: arg_size);
2404 ArgVTs.reserve(N: arg_size);
2405 ArgFlags.reserve(N: arg_size);
2406 for (auto ArgI = CI->arg_begin(), ArgE = CI->arg_end(); ArgI != ArgE; ++ArgI) {
2407 // If we're lowering a memory intrinsic instead of a regular call, skip the
2408 // last argument, which shouldn't be passed to the underlying function.
2409 if (IntrMemName && ArgE - ArgI <= 1)
2410 break;
2411
2412 ISD::ArgFlagsTy Flags;
2413 unsigned ArgIdx = ArgI - CI->arg_begin();
2414 if (CI->paramHasAttr(ArgIdx, Attribute::SExt))
2415 Flags.setSExt();
2416 if (CI->paramHasAttr(ArgIdx, Attribute::ZExt))
2417 Flags.setZExt();
2418
2419 // FIXME: Only handle *easy* calls for now.
2420 if (CI->paramHasAttr(ArgIdx, Attribute::InReg) ||
2421 CI->paramHasAttr(ArgIdx, Attribute::StructRet) ||
2422 CI->paramHasAttr(ArgIdx, Attribute::SwiftSelf) ||
2423 CI->paramHasAttr(ArgIdx, Attribute::SwiftError) ||
2424 CI->paramHasAttr(ArgIdx, Attribute::Nest) ||
2425 CI->paramHasAttr(ArgIdx, Attribute::ByVal))
2426 return false;
2427
2428 Type *ArgTy = (*ArgI)->getType();
2429 MVT ArgVT;
2430 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2431 ArgVT != MVT::i1)
2432 return false;
2433
2434 Register Arg = getRegForValue(V: *ArgI);
2435 if (!Arg.isValid())
2436 return false;
2437
2438 Flags.setOrigAlign(DL.getABITypeAlign(Ty: ArgTy));
2439
2440 Args.push_back(Elt: *ArgI);
2441 ArgRegs.push_back(Elt: Arg);
2442 ArgVTs.push_back(Elt: ArgVT);
2443 ArgFlags.push_back(Elt: Flags);
2444 }
2445
2446 // Handle the arguments now that we've gotten them.
2447 SmallVector<Register, 4> RegArgs;
2448 unsigned NumBytes;
2449 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2450 RegArgs, CC, NumBytes, isVarArg))
2451 return false;
2452
2453 bool UseReg = false;
2454 const GlobalValue *GV = dyn_cast<GlobalValue>(Val: Callee);
2455 if (!GV || Subtarget->genLongCalls()) UseReg = true;
2456
2457 Register CalleeReg;
2458 if (UseReg) {
2459 if (IntrMemName)
2460 CalleeReg = getLibcallReg(Name: IntrMemName);
2461 else
2462 CalleeReg = getRegForValue(V: Callee);
2463
2464 if (!CalleeReg)
2465 return false;
2466 }
2467
2468 // Issue the call.
2469 unsigned CallOpc = ARMSelectCallOp(UseReg);
2470 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt,
2471 MIMD, MCID: TII.get(Opcode: CallOpc));
2472
2473 // ARM calls don't take a predicate, but tBL / tBLX do.
2474 if(isThumb2)
2475 MIB.add(MOs: predOps(Pred: ARMCC::AL));
2476 if (UseReg) {
2477 CalleeReg =
2478 constrainOperandRegClass(II: TII.get(Opcode: CallOpc), Op: CalleeReg, OpNum: isThumb2 ? 2 : 0);
2479 MIB.addReg(RegNo: CalleeReg);
2480 } else if (!IntrMemName)
2481 MIB.addGlobalAddress(GV, Offset: 0, TargetFlags: 0);
2482 else
2483 MIB.addExternalSymbol(FnName: IntrMemName, TargetFlags: 0);
2484
2485 // Add implicit physical register uses to the call.
2486 for (Register R : RegArgs)
2487 MIB.addReg(RegNo: R, flags: RegState::Implicit);
2488
2489 // Add a register mask with the call-preserved registers.
2490 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2491 MIB.addRegMask(Mask: TRI.getCallPreservedMask(MF: *FuncInfo.MF, CC));
2492
2493 // Finish off the call including any return values.
2494 SmallVector<Register, 4> UsedRegs;
2495 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2496 return false;
2497
2498 // Set all unused physreg defs as dead.
2499 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2500
2501 return true;
2502}
2503
2504bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2505 return Len <= 16;
2506}
2507
2508bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
2509 MaybeAlign Alignment) {
2510 // Make sure we don't bloat code by inlining very large memcpy's.
2511 if (!ARMIsMemCpySmall(Len))
2512 return false;
2513
2514 while (Len) {
2515 MVT VT;
2516 if (!Alignment || *Alignment >= 4) {
2517 if (Len >= 4)
2518 VT = MVT::i32;
2519 else if (Len >= 2)
2520 VT = MVT::i16;
2521 else {
2522 assert(Len == 1 && "Expected a length of 1!");
2523 VT = MVT::i8;
2524 }
2525 } else {
2526 assert(Alignment && "Alignment is set in this branch");
2527 // Bound based on alignment.
2528 if (Len >= 2 && *Alignment == 2)
2529 VT = MVT::i16;
2530 else {
2531 VT = MVT::i8;
2532 }
2533 }
2534
2535 bool RV;
2536 Register ResultReg;
2537 RV = ARMEmitLoad(VT, ResultReg, Addr&: Src);
2538 assert(RV && "Should be able to handle this load.");
2539 RV = ARMEmitStore(VT, SrcReg: ResultReg, Addr&: Dest);
2540 assert(RV && "Should be able to handle this store.");
2541 (void)RV;
2542
2543 unsigned Size = VT.getSizeInBits()/8;
2544 Len -= Size;
2545 Dest.setOffset(Dest.getOffset() + Size);
2546 Src.setOffset(Src.getOffset() + Size);
2547 }
2548
2549 return true;
2550}
2551
2552bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2553 // FIXME: Handle more intrinsics.
2554 switch (I.getIntrinsicID()) {
2555 default: return false;
2556 case Intrinsic::frameaddress: {
2557 MachineFrameInfo &MFI = FuncInfo.MF->getFrameInfo();
2558 MFI.setFrameAddressIsTaken(true);
2559
2560 unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
2561 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
2562 : &ARM::GPRRegClass;
2563
2564 const ARMBaseRegisterInfo *RegInfo =
2565 static_cast<const ARMBaseRegisterInfo *>(Subtarget->getRegisterInfo());
2566 Register FramePtr = RegInfo->getFrameRegister(MF: *(FuncInfo.MF));
2567 Register SrcReg = FramePtr;
2568
2569 // Recursively load frame address
2570 // ldr r0 [fp]
2571 // ldr r0 [r0]
2572 // ldr r0 [r0]
2573 // ...
2574 Register DestReg;
2575 unsigned Depth = cast<ConstantInt>(Val: I.getOperand(i_nocapture: 0))->getZExtValue();
2576 while (Depth--) {
2577 DestReg = createResultReg(RC);
2578 AddOptionalDefs(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2579 MCID: TII.get(Opcode: LdrOpc), DestReg)
2580 .addReg(RegNo: SrcReg).addImm(Val: 0));
2581 SrcReg = DestReg;
2582 }
2583 updateValueMap(I: &I, Reg: SrcReg);
2584 return true;
2585 }
2586 case Intrinsic::memcpy:
2587 case Intrinsic::memmove: {
2588 const MemTransferInst &MTI = cast<MemTransferInst>(Val: I);
2589 // Don't handle volatile.
2590 if (MTI.isVolatile())
2591 return false;
2592
2593 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2594 // we would emit dead code because we don't currently handle memmoves.
2595 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2596 if (isa<ConstantInt>(Val: MTI.getLength()) && isMemCpy) {
2597 // Small memcpy's are common enough that we want to do them without a call
2598 // if possible.
2599 uint64_t Len = cast<ConstantInt>(Val: MTI.getLength())->getZExtValue();
2600 if (ARMIsMemCpySmall(Len)) {
2601 Address Dest, Src;
2602 if (!ARMComputeAddress(Obj: MTI.getRawDest(), Addr&: Dest) ||
2603 !ARMComputeAddress(Obj: MTI.getRawSource(), Addr&: Src))
2604 return false;
2605 MaybeAlign Alignment;
2606 if (MTI.getDestAlign() || MTI.getSourceAlign())
2607 Alignment = std::min(a: MTI.getDestAlign().valueOrOne(),
2608 b: MTI.getSourceAlign().valueOrOne());
2609 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2610 return true;
2611 }
2612 }
2613
2614 if (!MTI.getLength()->getType()->isIntegerTy(Bitwidth: 32))
2615 return false;
2616
2617 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2618 return false;
2619
2620 const char *IntrMemName = isa<MemCpyInst>(Val: I) ? "memcpy" : "memmove";
2621 return SelectCall(I: &I, IntrMemName);
2622 }
2623 case Intrinsic::memset: {
2624 const MemSetInst &MSI = cast<MemSetInst>(Val: I);
2625 // Don't handle volatile.
2626 if (MSI.isVolatile())
2627 return false;
2628
2629 if (!MSI.getLength()->getType()->isIntegerTy(Bitwidth: 32))
2630 return false;
2631
2632 if (MSI.getDestAddressSpace() > 255)
2633 return false;
2634
2635 return SelectCall(I: &I, IntrMemName: "memset");
2636 }
2637 case Intrinsic::trap: {
2638 unsigned Opcode;
2639 if (Subtarget->isThumb())
2640 Opcode = ARM::tTRAP;
2641 else
2642 Opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
2643 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode));
2644 return true;
2645 }
2646 }
2647}
2648
2649bool ARMFastISel::SelectTrunc(const Instruction *I) {
2650 // The high bits for a type smaller than the register size are assumed to be
2651 // undefined.
2652 Value *Op = I->getOperand(i: 0);
2653
2654 EVT SrcVT, DestVT;
2655 SrcVT = TLI.getValueType(DL, Ty: Op->getType(), AllowUnknown: true);
2656 DestVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
2657
2658 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2659 return false;
2660 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2661 return false;
2662
2663 Register SrcReg = getRegForValue(V: Op);
2664 if (!SrcReg) return false;
2665
2666 // Because the high bits are undefined, a truncate doesn't generate
2667 // any code.
2668 updateValueMap(I, Reg: SrcReg);
2669 return true;
2670}
2671
2672Register ARMFastISel::ARMEmitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT,
2673 bool isZExt) {
2674 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2675 return Register();
2676 if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2677 return Register();
2678
2679 // Table of which combinations can be emitted as a single instruction,
2680 // and which will require two.
2681 static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2682 // ARM Thumb
2683 // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops
2684 // ext: s z s z s z s z
2685 /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2686 /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2687 /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2688 };
2689
2690 // Target registers for:
2691 // - For ARM can never be PC.
2692 // - For 16-bit Thumb are restricted to lower 8 registers.
2693 // - For 32-bit Thumb are restricted to non-SP and non-PC.
2694 static const TargetRegisterClass *RCTbl[2][2] = {
2695 // Instructions: Two Single
2696 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2697 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2698 };
2699
2700 // Table governing the instruction(s) to be emitted.
2701 static const struct InstructionTable {
2702 uint32_t Opc : 16;
2703 uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0.
2704 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi.
2705 uint32_t Imm : 8; // All instructions have either a shift or a mask.
2706 } IT[2][2][3][2] = {
2707 { // Two instructions (first is left shift, second is in this table).
2708 { // ARM Opc S Shift Imm
2709 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2710 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2711 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2712 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2713 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2714 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2715 },
2716 { // Thumb Opc S Shift Imm
2717 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2718 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2719 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2720 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2721 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2722 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2723 }
2724 },
2725 { // Single instruction.
2726 { // ARM Opc S Shift Imm
2727 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2728 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2729 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2730 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2731 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2732 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2733 },
2734 { // Thumb Opc S Shift Imm
2735 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2736 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2737 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2738 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2739 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2740 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2741 }
2742 }
2743 };
2744
2745 unsigned SrcBits = SrcVT.getSizeInBits();
2746 unsigned DestBits = DestVT.getSizeInBits();
2747 (void) DestBits;
2748 assert((SrcBits < DestBits) && "can only extend to larger types");
2749 assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2750 "other sizes unimplemented");
2751 assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2752 "other sizes unimplemented");
2753
2754 bool hasV6Ops = Subtarget->hasV6Ops();
2755 unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2}
2756 assert((Bitness < 3) && "sanity-check table bounds");
2757
2758 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2759 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2760 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2761 unsigned Opc = ITP->Opc;
2762 assert(ARM::KILL != Opc && "Invalid table entry");
2763 unsigned hasS = ITP->hasS;
2764 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2765 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2766 "only MOVsi has shift operand addressing mode");
2767 unsigned Imm = ITP->Imm;
2768
2769 // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2770 bool setsCPSR = &ARM::tGPRRegClass == RC;
2771 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2772 Register ResultReg;
2773 // MOVsi encodes shift and immediate in shift operand addressing mode.
2774 // The following condition has the same value when emitting two
2775 // instruction sequences: both are shifts.
2776 bool ImmIsSO = (Shift != ARM_AM::no_shift);
2777
2778 // Either one or two instructions are emitted.
2779 // They're always of the form:
2780 // dst = in OP imm
2781 // CPSR is set only by 16-bit Thumb instructions.
2782 // Predicate, if any, is AL.
2783 // S bit, if available, is always 0.
2784 // When two are emitted the first's result will feed as the second's input,
2785 // that value is then dead.
2786 unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2787 for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2788 ResultReg = createResultReg(RC);
2789 bool isLsl = (0 == Instr) && !isSingleInstr;
2790 unsigned Opcode = isLsl ? LSLOpc : Opc;
2791 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2792 unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShOp: ShiftAM, Imm) : Imm;
2793 bool isKill = 1 == Instr;
2794 MachineInstrBuilder MIB = BuildMI(
2795 BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode), DestReg: ResultReg);
2796 if (setsCPSR)
2797 MIB.addReg(ARM::CPSR, RegState::Define);
2798 SrcReg = constrainOperandRegClass(II: TII.get(Opcode), Op: SrcReg, OpNum: 1 + setsCPSR);
2799 MIB.addReg(RegNo: SrcReg, flags: isKill * RegState::Kill)
2800 .addImm(Val: ImmEnc)
2801 .add(MOs: predOps(Pred: ARMCC::AL));
2802 if (hasS)
2803 MIB.add(MO: condCodeOp());
2804 // Second instruction consumes the first's result.
2805 SrcReg = ResultReg;
2806 }
2807
2808 return ResultReg;
2809}
2810
2811bool ARMFastISel::SelectIntExt(const Instruction *I) {
2812 // On ARM, in general, integer casts don't involve legal types; this code
2813 // handles promotable integers.
2814 Type *DestTy = I->getType();
2815 Value *Src = I->getOperand(i: 0);
2816 Type *SrcTy = Src->getType();
2817
2818 bool isZExt = isa<ZExtInst>(Val: I);
2819 Register SrcReg = getRegForValue(V: Src);
2820 if (!SrcReg) return false;
2821
2822 EVT SrcEVT, DestEVT;
2823 SrcEVT = TLI.getValueType(DL, Ty: SrcTy, AllowUnknown: true);
2824 DestEVT = TLI.getValueType(DL, Ty: DestTy, AllowUnknown: true);
2825 if (!SrcEVT.isSimple()) return false;
2826 if (!DestEVT.isSimple()) return false;
2827
2828 MVT SrcVT = SrcEVT.getSimpleVT();
2829 MVT DestVT = DestEVT.getSimpleVT();
2830 Register ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2831 if (!ResultReg)
2832 return false;
2833 updateValueMap(I, Reg: ResultReg);
2834 return true;
2835}
2836
2837bool ARMFastISel::SelectShift(const Instruction *I,
2838 ARM_AM::ShiftOpc ShiftTy) {
2839 // We handle thumb2 mode by target independent selector
2840 // or SelectionDAG ISel.
2841 if (isThumb2)
2842 return false;
2843
2844 // Only handle i32 now.
2845 EVT DestVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
2846 if (DestVT != MVT::i32)
2847 return false;
2848
2849 unsigned Opc = ARM::MOVsr;
2850 unsigned ShiftImm;
2851 Value *Src2Value = I->getOperand(i: 1);
2852 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val: Src2Value)) {
2853 ShiftImm = CI->getZExtValue();
2854
2855 // Fall back to selection DAG isel if the shift amount
2856 // is zero or greater than the width of the value type.
2857 if (ShiftImm == 0 || ShiftImm >=32)
2858 return false;
2859
2860 Opc = ARM::MOVsi;
2861 }
2862
2863 Value *Src1Value = I->getOperand(i: 0);
2864 Register Reg1 = getRegForValue(V: Src1Value);
2865 if (!Reg1)
2866 return false;
2867
2868 Register Reg2;
2869 if (Opc == ARM::MOVsr) {
2870 Reg2 = getRegForValue(V: Src2Value);
2871 if (!Reg2)
2872 return false;
2873 }
2874
2875 Register ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2876 if (!ResultReg)
2877 return false;
2878
2879 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2880 MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
2881 .addReg(RegNo: Reg1);
2882
2883 if (Opc == ARM::MOVsi)
2884 MIB.addImm(Val: ARM_AM::getSORegOpc(ShOp: ShiftTy, Imm: ShiftImm));
2885 else if (Opc == ARM::MOVsr) {
2886 MIB.addReg(RegNo: Reg2);
2887 MIB.addImm(Val: ARM_AM::getSORegOpc(ShOp: ShiftTy, Imm: 0));
2888 }
2889
2890 AddOptionalDefs(MIB);
2891 updateValueMap(I, Reg: ResultReg);
2892 return true;
2893}
2894
2895// TODO: SoftFP support.
2896bool ARMFastISel::fastSelectInstruction(const Instruction *I) {
2897 switch (I->getOpcode()) {
2898 case Instruction::Load:
2899 return SelectLoad(I);
2900 case Instruction::Store:
2901 return SelectStore(I);
2902 case Instruction::Br:
2903 return SelectBranch(I);
2904 case Instruction::IndirectBr:
2905 return SelectIndirectBr(I);
2906 case Instruction::ICmp:
2907 case Instruction::FCmp:
2908 return SelectCmp(I);
2909 case Instruction::FPExt:
2910 return SelectFPExt(I);
2911 case Instruction::FPTrunc:
2912 return SelectFPTrunc(I);
2913 case Instruction::SIToFP:
2914 return SelectIToFP(I, /*isSigned*/ true);
2915 case Instruction::UIToFP:
2916 return SelectIToFP(I, /*isSigned*/ false);
2917 case Instruction::FPToSI:
2918 return SelectFPToI(I, /*isSigned*/ true);
2919 case Instruction::FPToUI:
2920 return SelectFPToI(I, /*isSigned*/ false);
2921 case Instruction::Add:
2922 return SelectBinaryIntOp(I, ISDOpcode: ISD::ADD);
2923 case Instruction::Or:
2924 return SelectBinaryIntOp(I, ISDOpcode: ISD::OR);
2925 case Instruction::Sub:
2926 return SelectBinaryIntOp(I, ISDOpcode: ISD::SUB);
2927 case Instruction::FAdd:
2928 return SelectBinaryFPOp(I, ISDOpcode: ISD::FADD);
2929 case Instruction::FSub:
2930 return SelectBinaryFPOp(I, ISDOpcode: ISD::FSUB);
2931 case Instruction::FMul:
2932 return SelectBinaryFPOp(I, ISDOpcode: ISD::FMUL);
2933 case Instruction::SDiv:
2934 return SelectDiv(I, /*isSigned*/ true);
2935 case Instruction::UDiv:
2936 return SelectDiv(I, /*isSigned*/ false);
2937 case Instruction::SRem:
2938 return SelectRem(I, /*isSigned*/ true);
2939 case Instruction::URem:
2940 return SelectRem(I, /*isSigned*/ false);
2941 case Instruction::Call:
2942 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(Val: I))
2943 return SelectIntrinsicCall(I: *II);
2944 return SelectCall(I);
2945 case Instruction::Select:
2946 return SelectSelect(I);
2947 case Instruction::Ret:
2948 return SelectRet(I);
2949 case Instruction::Trunc:
2950 return SelectTrunc(I);
2951 case Instruction::ZExt:
2952 case Instruction::SExt:
2953 return SelectIntExt(I);
2954 case Instruction::Shl:
2955 return SelectShift(I, ShiftTy: ARM_AM::lsl);
2956 case Instruction::LShr:
2957 return SelectShift(I, ShiftTy: ARM_AM::lsr);
2958 case Instruction::AShr:
2959 return SelectShift(I, ShiftTy: ARM_AM::asr);
2960 default: break;
2961 }
2962 return false;
2963}
2964
2965// This table describes sign- and zero-extend instructions which can be
2966// folded into a preceding load. All of these extends have an immediate
2967// (sometimes a mask and sometimes a shift) that's applied after
2968// extension.
2969static const struct FoldableLoadExtendsStruct {
2970 uint16_t Opc[2]; // ARM, Thumb.
2971 uint8_t ExpectedImm;
2972 uint8_t isZExt : 1;
2973 uint8_t ExpectedVT : 7;
2974} FoldableLoadExtends[] = {
2975 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2976 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2977 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2978 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2979 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
2980};
2981
2982/// The specified machine instr operand is a vreg, and that
2983/// vreg is being provided by the specified load instruction. If possible,
2984/// try to fold the load as an operand to the instruction, returning true if
2985/// successful.
2986bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2987 const LoadInst *LI) {
2988 // Verify we have a legal type before going any further.
2989 MVT VT;
2990 if (!isLoadTypeLegal(Ty: LI->getType(), VT))
2991 return false;
2992
2993 // Combine load followed by zero- or sign-extend.
2994 // ldrb r1, [r0] ldrb r1, [r0]
2995 // uxtb r2, r1 =>
2996 // mov r3, r2 mov r3, r1
2997 if (MI->getNumOperands() < 3 || !MI->getOperand(i: 2).isImm())
2998 return false;
2999 const uint64_t Imm = MI->getOperand(i: 2).getImm();
3000
3001 bool Found = false;
3002 bool isZExt;
3003 for (const FoldableLoadExtendsStruct &FLE : FoldableLoadExtends) {
3004 if (FLE.Opc[isThumb2] == MI->getOpcode() &&
3005 (uint64_t)FLE.ExpectedImm == Imm &&
3006 MVT((MVT::SimpleValueType)FLE.ExpectedVT) == VT) {
3007 Found = true;
3008 isZExt = FLE.isZExt;
3009 }
3010 }
3011 if (!Found) return false;
3012
3013 // See if we can handle this address.
3014 Address Addr;
3015 if (!ARMComputeAddress(Obj: LI->getOperand(i_nocapture: 0), Addr)) return false;
3016
3017 Register ResultReg = MI->getOperand(i: 0).getReg();
3018 if (!ARMEmitLoad(VT, ResultReg, Addr, Alignment: LI->getAlign(), isZExt, allocReg: false))
3019 return false;
3020 MachineBasicBlock::iterator I(MI);
3021 removeDeadCode(I, E: std::next(x: I));
3022 return true;
3023}
3024
3025Register ARMFastISel::ARMLowerPICELF(const GlobalValue *GV, MVT VT) {
3026 bool UseGOT_PREL = !GV->isDSOLocal();
3027 LLVMContext *Context = &MF->getFunction().getContext();
3028 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3029 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3030 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(
3031 C: GV, ID: ARMPCLabelIndex, Kind: ARMCP::CPValue, PCAdj,
3032 Modifier: UseGOT_PREL ? ARMCP::GOT_PREL : ARMCP::no_modifier,
3033 /*AddCurrentAddress=*/UseGOT_PREL);
3034
3035 Align ConstAlign =
3036 MF->getDataLayout().getPrefTypeAlign(Ty: PointerType::get(C&: *Context, AddressSpace: 0));
3037 unsigned Idx = MF->getConstantPool()->getConstantPoolIndex(V: CPV, Alignment: ConstAlign);
3038 MachineMemOperand *CPMMO =
3039 MF->getMachineMemOperand(PtrInfo: MachinePointerInfo::getConstantPool(MF&: *MF),
3040 F: MachineMemOperand::MOLoad, Size: 4, BaseAlignment: Align(4));
3041
3042 Register TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
3043 unsigned Opc = isThumb2 ? ARM::t2LDRpci : ARM::LDRcp;
3044 MachineInstrBuilder MIB =
3045 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: TempReg)
3046 .addConstantPoolIndex(Idx)
3047 .addMemOperand(MMO: CPMMO);
3048 if (Opc == ARM::LDRcp)
3049 MIB.addImm(Val: 0);
3050 MIB.add(MOs: predOps(Pred: ARMCC::AL));
3051
3052 // Fix the address by adding pc.
3053 Register DestReg = createResultReg(RC: TLI.getRegClassFor(VT));
3054 Opc = Subtarget->isThumb() ? ARM::tPICADD : UseGOT_PREL ? ARM::PICLDR
3055 : ARM::PICADD;
3056 DestReg = constrainOperandRegClass(II: TII.get(Opcode: Opc), Op: DestReg, OpNum: 0);
3057 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg)
3058 .addReg(RegNo: TempReg)
3059 .addImm(Val: ARMPCLabelIndex);
3060
3061 if (!Subtarget->isThumb())
3062 MIB.add(MOs: predOps(Pred: ARMCC::AL));
3063
3064 if (UseGOT_PREL && Subtarget->isThumb()) {
3065 Register NewDestReg = createResultReg(RC: TLI.getRegClassFor(VT));
3066 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
3067 TII.get(ARM::t2LDRi12), NewDestReg)
3068 .addReg(DestReg)
3069 .addImm(0);
3070 DestReg = NewDestReg;
3071 AddOptionalDefs(MIB);
3072 }
3073 return DestReg;
3074}
3075
3076bool ARMFastISel::fastLowerArguments() {
3077 if (!FuncInfo.CanLowerReturn)
3078 return false;
3079
3080 const Function *F = FuncInfo.Fn;
3081 if (F->isVarArg())
3082 return false;
3083
3084 CallingConv::ID CC = F->getCallingConv();
3085 switch (CC) {
3086 default:
3087 return false;
3088 case CallingConv::Fast:
3089 case CallingConv::C:
3090 case CallingConv::ARM_AAPCS_VFP:
3091 case CallingConv::ARM_AAPCS:
3092 case CallingConv::ARM_APCS:
3093 case CallingConv::Swift:
3094 case CallingConv::SwiftTail:
3095 break;
3096 }
3097
3098 // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3099 // which are passed in r0 - r3.
3100 for (const Argument &Arg : F->args()) {
3101 if (Arg.getArgNo() >= 4)
3102 return false;
3103
3104 if (Arg.hasAttribute(Attribute::InReg) ||
3105 Arg.hasAttribute(Attribute::StructRet) ||
3106 Arg.hasAttribute(Attribute::SwiftSelf) ||
3107 Arg.hasAttribute(Attribute::SwiftError) ||
3108 Arg.hasAttribute(Attribute::ByVal))
3109 return false;
3110
3111 Type *ArgTy = Arg.getType();
3112 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3113 return false;
3114
3115 EVT ArgVT = TLI.getValueType(DL, Ty: ArgTy);
3116 if (!ArgVT.isSimple()) return false;
3117 switch (ArgVT.getSimpleVT().SimpleTy) {
3118 case MVT::i8:
3119 case MVT::i16:
3120 case MVT::i32:
3121 break;
3122 default:
3123 return false;
3124 }
3125 }
3126
3127 static const MCPhysReg GPRArgRegs[] = {
3128 ARM::R0, ARM::R1, ARM::R2, ARM::R3
3129 };
3130
3131 const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3132 for (const Argument &Arg : F->args()) {
3133 unsigned ArgNo = Arg.getArgNo();
3134 MCRegister SrcReg = GPRArgRegs[ArgNo];
3135 Register DstReg = FuncInfo.MF->addLiveIn(PReg: SrcReg, RC);
3136 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3137 // Without this, EmitLiveInCopies may eliminate the livein if its only
3138 // use is a bitcast (which isn't turned into an instruction).
3139 Register ResultReg = createResultReg(RC);
3140 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
3141 MCID: TII.get(Opcode: TargetOpcode::COPY),
3142 DestReg: ResultReg).addReg(RegNo: DstReg, flags: getKillRegState(B: true));
3143 updateValueMap(I: &Arg, Reg: ResultReg);
3144 }
3145
3146 return true;
3147}
3148
3149namespace llvm {
3150
3151 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3152 const TargetLibraryInfo *libInfo) {
3153 if (funcInfo.MF->getSubtarget<ARMSubtarget>().useFastISel())
3154 return new ARMFastISel(funcInfo, libInfo);
3155
3156 return nullptr;
3157 }
3158
3159} // end namespace llvm
3160

Provided by KDAB

Privacy Policy
Learn to use CMake with our Intro Training
Find out more

source code of llvm/lib/Target/ARM/ARMFastISel.cpp